公开(公告)号：US20100329403A1

公开(公告)日：2010-12-30

申请号：US12492419

申请日：2009-06-26

申请人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

发明人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

IPC分类号： H04L7/00

CPC分类号： H03K5/1565 ,  H03K5/15013 ,  H03K2005/00052

摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。

公开(公告)号：US08139700B2

公开(公告)日：2012-03-20

申请号：US12492419

申请日：2009-06-26

申请人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

发明人： Troy J. Beukema ,  Steven M. Clements ,  Chun-Ming Hsu ,  William R. Kelly ,  Elizabeth M. May ,  Sergey V. Rylov

IPC分类号： H04L25/00

CPC分类号： H03K5/1565 ,  H03K5/15013 ,  H03K2005/00052

摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.

摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。