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公开(公告)号：US08139700B2
公开(公告)日：2012-03-20
申请号：US12492419
申请日：2009-06-26
申请人： Troy J. Beukema , Steven M. Clements , Chun-Ming Hsu , William R. Kelly , Elizabeth M. May , Sergey V. Rylov
发明人： Troy J. Beukema , Steven M. Clements , Chun-Ming Hsu , William R. Kelly , Elizabeth M. May , Sergey V. Rylov
IPC分类号： H04L25/00
CPC分类号： H03K5/1565 , H03K5/15013 , H03K2005/00052
摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.
摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。
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公开(公告)号：US20100329403A1
公开(公告)日：2010-12-30
申请号：US12492419
申请日：2009-06-26
申请人： Troy J. Beukema , Steven M. Clements , Chun-Ming Hsu , William R. Kelly , Elizabeth M. May , Sergey V. Rylov
发明人： Troy J. Beukema , Steven M. Clements , Chun-Ming Hsu , William R. Kelly , Elizabeth M. May , Sergey V. Rylov
IPC分类号： H04L7/00
CPC分类号： H03K5/1565 , H03K5/15013 , H03K2005/00052
摘要： A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.
摘要翻译： 用于闭环时钟校正的系统和方法包括调整包括至少一个同相时钟和一个正交时钟的两个或更多个输入信号，并将调整的正交时钟信号应用于能够产生4象限内插输出时钟相位的器件。 内插输出时钟相位被延迟以形成用于测量设备的时钟。 在内插输出时钟相位的范围内，在测量装置上测量两个或多个调整后的输入信号。 使用来自测量装置的采样信息，在同相时钟和正交时钟上确定错误。 使用确定的误差信息适配同相时钟和正交时钟。
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3.发明授权公开(公告)号：US08401135B2
公开(公告)日：2013-03-19
申请号：US12698629
申请日：2010-02-02
IPC分类号： H04B1/10
CPC分类号： H04L27/01
摘要： A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.
摘要翻译： 串行数据接收器包括幅度路径，该幅度路径包括基于选择输入添加第一偏移或减去第二偏移的第一信号调节器，被配置为从发送器接收信号并且向幅度路径提供输入信号的前置放大器， 耦合到振幅路径的振幅锁存器，具有数据输出的数据锁存器和耦合到第一调理元件和数据输出的判定反馈均衡（DFE）逻辑块，并且被配置为基于数据的数据输出生成选择输出 锁定。
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4.发明申请公开(公告)号：US20110188566A1
公开(公告)日：2011-08-04
申请号：US12698629
申请日：2010-02-02
IPC分类号： H04L27/01
CPC分类号： H04L27/01
摘要： A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.
摘要翻译： 串行数据接收器包括幅度路径，该幅度路径包括基于选择输入添加第一偏移或减去第二偏移的第一信号调节器，被配置为从发送器接收信号并且向幅度路径提供输入信号的前置放大器， 耦合到振幅路径的振幅锁存器，具有数据输出的数据锁存器和耦合到第一调理元件和数据输出的判定反馈均衡（DFE）逻辑块，并且被配置为基于数据的数据输出生成选择输出 锁定。
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公开(公告)号：US08964825B2
公开(公告)日：2015-02-24
申请号：US13399675
申请日：2012-02-17
CPC分类号： G06G7/184 , H03F3/45098 , H03F2203/45296 , H03F2203/45298 , H03F2203/45374 , H03F2203/45466 , H03F2203/45616 , H03F2203/45618 , H04L25/0296 , H04L25/03885
摘要： Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.
摘要翻译： 模拟信号电流积分器具有可调峰值功能。 具有可调谐峰值功能的模拟信号电流积分器可实现数据速率相关的损耗补偿，适用于包含高级均衡功能的高数据速率接收机集成电路中的应用，如决策反馈均衡器。 例如，电流积分器电路包括电流积分放大器电路，该电流积分放大器电路包括调整电路元件以调节电流积分器电路的峰值响应，以及峰化控制电路，用于产生控制信号，以将可调节电路元件的值调整为 当前积分器电路的工作状态的功能。 操作条件可以是指定的数据速率或通信信道特性，也可以是两者。 可调电路元件可以是退化电容器或偏置电流源。
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公开(公告)号：US08599966B2
公开(公告)日：2013-12-03
申请号：US13173434
申请日：2011-06-30
CPC分类号： H03F3/45695 , H03F1/02 , H03G3/3089 , H04L25/0296
摘要： A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.
摘要翻译： 公开了一种数据接收器，操作数据接收器的方法和数据接收器中的集成耦合系统。 在一个实施例中，数据接收器包括用于接收输入数据信号的输入端，用于放大输入数据信号的选定分量的输入放大器和用于传输指定高频分量的输入信号路径和输入的基线分量 数据信号从输入端到输入放大器。 数据接收器还包括连接到输入端和输入放大器的前馈电阻网络。 该前馈电阻网络用于使用无源电阻网络将低频漂移补偿信号从输入端子转发到输入放大器，以补偿输入数据信号中的低频变化，并产生所需的偏置电压 在输入放大器。
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7.发明授权Receiver and integrated AM-FM/IQ demodulators for gigabit-rate data detection 有权接收器和集成AM-FM / IQ解调器，用于千兆比特率数据检测公开(公告)号：US08543079B2
公开(公告)日：2013-09-24
申请号：US13589680
申请日：2012-08-20
申请人： Troy J. Beukema , Scott K. Reynolds
发明人： Troy J. Beukema , Scott K. Reynolds
IPC分类号： H04B1/28
摘要： Provision of gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. Disclosed herein are architecture for supporting both quadrature down-conversion and ASK/AM, ASK/AM detector circuit details, AM-FM detector architecture, and an AM-FM/IQ demodulator system and FSK/FM detector circuit details.
摘要翻译： 通过毫米波范围（> 30 GHz）的载波频率，通过无线无线电链路提供千兆比特数据传输。 更具体地，描述了用于检测可以容易地并入到集成电路接收机系统中的幅移键控（ASK）或其他幅度调制（AM）的电路，使得接收机能够支持复合IQ调制方案和更简单， 非相干开关或多电平键控信号。 还描述了几种新颖的无线电架构，其中通过添加鉴频器网络具有处理频移键控（FSK）或其他频率调制（FM）以及AM和复杂IQ调制方案的能力。 这些无线电架构通过有效地共享检测器硬件组件来支持这种广泛的调制。 这里公开了用于支持正交下变频和ASK / AM，ASK / AM检测器电路细节，AM-FM检测器架构以及AM-FM / IQ解调器系统和FSK / FM检测器电路细节的架构。
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8.发明申请RECEIVER AND INTEGRATED AM-FM/IQ DEMODULATORS FOR GIGABIT-RATE DATA DETECTION 有权接收器和集成AM-FM / IQ解调器用于数据速率数据检测公开(公告)号：US20080280577A1
公开(公告)日：2008-11-13
申请号：US12177252
申请日：2008-07-22
申请人： Troy J. Beukema , Scott K. Reynolds
发明人： Troy J. Beukema , Scott K. Reynolds
IPC分类号： H04B1/18
摘要： This disclosure addresses providing gigabit-rate data transmission over wireless radio links, using carrier frequencies in the millimeter-wave range (>30 GHz). More specifically, a circuit for detection of amplitude-shift keyed (ASK) or other amplitude modulations (AM) which can be easily incorporated into an integrated circuit receiver system is described, making the receiver capable of supporting both complex IQ modulation schemes and simpler, non-coherent on-off or multiple-level keying signals. Several novel radio architectures are also described which, with the addition of a frequency discriminator network, have the capability of handling frequency shift keyed (FSK) or other frequency modulations (FM), as well as AM and complex IQ modulation schemes. These radio architectures support this wide variety of modulations by efficiently sharing detector hardware components. The architecture for supporting both quadrature down-conversion and ASK/AM is described first, followed by the ASK/AM detector circuit details, then the AM-FM detector architecture, and finally the most general AM-FM/IQ demodulator system concept and the FSK/FM detector circuit details.
摘要翻译： 本公开涉及使用毫米波范围（> 30GHz）中的载波频率，通过无线无线电链路提供千兆比特数据传输。 更具体地，描述了用于检测可以容易地并入到集成电路接收机系统中的幅移键控（ASK）或其他幅度调制（AM）的电路，使得接收机能够支持复合IQ调制方案和更简单， 非相干开关或多电平键控信号。 还描述了几种新颖的无线电架构，其中通过添加鉴频器网络具有处理频移键控（FSK）或其他频率调制（FM）以及AM和复杂IQ调制方案的能力。 这些无线电架构通过有效地共享检测器硬件组件来支持这种广泛的调制。 首先描述支持正交下变频和ASK / AM的架构，其次是ASK / AM检波器电路细节，然后是AM-FM检测器架构，最后是最通用的AM-FM / IQ解调器系统概念和 FSK / FM检测电路的细节。
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9.发明授权公开(公告)号：US06393083B1
公开(公告)日：2002-05-21
申请号：US09126990
申请日：1998-07-31
申请人： Troy J. Beukema
发明人： Troy J. Beukema
IPC分类号： H04L2500
CPC分类号： H03H17/08 , H04L2027/0063
摘要： An apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital Multipliers. The digital phase shifter operates by applying a phase correction to complex digital I/Q samples in separate stages, where each stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase. In one aspect, an apparatus for applying a phase shift to a complex digital signal comprises a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of the plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.
摘要翻译： 一种用于数字移相器的改进的硬件实现的装置和方法，其提供用于数字信号的相位校正的简化过程，并且消除了使用查找ROM和复数数字乘法器。 数字移相器通过对分立阶段的复数数字I / Q采样施加相位校正来进行操作，其中每个级通过整数输入相位的二进制值直接指定的量进行相位旋转。 在一个方面，一种用于向复数数字信号施加相移的装置包括多个相移级，每个相移级具有与其相关联的相移值，由此多个相移级中的每一个选择性地将对应的相移值施加到 复杂的数字信号。
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公开(公告)号：US20130215954A1
公开(公告)日：2013-08-22
申请号：US13399675
申请日：2012-02-17
CPC分类号： G06G7/184 , H03F3/45098 , H03F2203/45296 , H03F2203/45298 , H03F2203/45374 , H03F2203/45466 , H03F2203/45616 , H03F2203/45618 , H04L25/0296 , H04L25/03885
摘要： Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.
摘要翻译： 模拟信号电流积分器具有可调峰值功能。 具有可调谐峰值功能的模拟信号电流积分器可实现数据速率相关的损耗补偿，适用于包含高级均衡功能的高数据速率接收机集成电路中的应用，如决策反馈均衡器。 例如，电流积分器电路包括电流积分放大器电路，该电流积分放大器电路包括调整电路元件以调节电流积分器电路的峰值响应，以及峰值控制电路，用于产生控制信号，以将可调节电路元件的值调整为 当前积分器电路的工作状态的功能。 操作条件可以是指定的数据速率或通信信道特性，也可以是两者。 可调电路元件可以是退化电容器或偏置电流源。
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