公开(公告)号：US20060222136A1

公开(公告)日：2006-10-05

申请号：US11097577

申请日：2005-04-01

Applicant: Mahibur Rahman ,  Emilio Quiroga

Inventor： Mahibur Rahman ,  Emilio Quiroga

IPC: H04L7/00 ,  H03D3/24

CPC classification number: H04L7/0338 ,  H04L7/04

Abstract: Methods, devices and systems are provided for bit synchronizing multiple serial bitstreams (106) with a common clock signal (116). Activity occurring in each bitstream is detected (304) for each of a plurality of phases corresponding to cycles of the common clock signal. One of the plurality of phases is selected (308) for each of the serial bitstreams based upon the activity detected within the selected phase. Data is then extracted (322) from the selected phase for each of the serial bitstreams using the common clock signal to thereby bit synchronize each of the plurality of serial bitstreams to each other.

Abstract translation: 提供方法，装置和系统用于将多个串行位流（106）与公共时钟信号（116）进行位同步。 对于与公共时钟信号的周期相对应的多个相位中的每一个，检测出每个比特流中发生的活动（304）。 基于在所选择的相位内检测到的活动，为每个串行比特流选择多个相位中的一个（308）。 然后使用公共时钟信号从针对每个串行比特流的所选择的相位提取数据（322），从而将多个串行比特流中的每一个相互同步。

公开(公告)号：US20060222017A1

公开(公告)日：2006-10-05

申请号：US11097579

申请日：2005-04-01

Applicant: Emilio Quiroga ,  Mahibur Rahman

Inventor： Emilio Quiroga ,  Mahibur Rahman

IPC: H04J3/06

CPC classification number: H04J3/0605 ,  H04J3/047 ,  H04L7/0338

Abstract: Methods, devices and systems are provided for word synchronizing multiple serial data bitstreams (106) with a serial framing signal (106A). Offset values (420) are determined (512) from the relative locations of predetermined data correlation values (107) stored within the data buffers during a correlation mode to indicate the amount of skew observed between the framing channel and each of serial data channels. Data received during subsequent operation of each data stream is stored a buffer (402), and the framing signal (106A) is monitored to identify a boundary between data words. When a frame boundary occurs, parallel data is extracted from the buffer using the previously-stored offset values to compensate for bit skew between the data and framing channels.

Abstract translation: 提供方法，装置和系统用于使串行成帧信号（106A）的多个串行数据比特流（106）进行字同步。 在相关模式期间从存储在数据缓冲器内的预定数据相关值（107）的相对位置确定偏移值（420）（512），以指示在成帧通道和每个串行数据通道之间观察到的偏斜量。 在每个数据流的后续操作期间接收的数据被存储在缓冲器（402）中，并且监视成帧信号（106A）以识别数据字之间的边界。 当发生帧边界时，使用先前存储的偏移值从缓冲器中提取并行数据，以补偿数据和成帧通道之间的位偏移。

公开(公告)号：US20100111154A1

公开(公告)日：2010-05-06

申请号：US12522043

申请日：2007-01-09

Applicant: Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe ,  Emilio Quiroga ,  Samir Soni

Inventor： Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe ,  Emilio Quiroga ,  Samir Soni

IPC: H04L27/00 ,  H04B17/00

CPC classification number: H04L7/0338 ,  H04L7/042

Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Abstract translation: 无线通信设备包括多个子系统和时钟生成逻辑，其布置成生成要应用于子系统数量的至少一个时钟信号。 子系统的数量之一包括用于接收输入数据的采样逻辑，并且使用施加到采样逻辑的至少一个时钟信号的时钟周期的多个分离相位对输入数据位执行初始采样，从而产生多相分离采样 输入数据位的输出。 采样逻辑被配置为在多个中间相位的多相分离采样输出上执行多个重采样操作，从而在执行多相分离中间采样输出的最终采样之前产生多相分离中间采样输出 所述至少一个时钟信号的单相以产生采样的输入数据信号。

公开(公告)号：US08306172B2

公开(公告)日：2012-11-06

申请号：US12522043

申请日：2007-01-09

Applicant: Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe ,  Emilio Quiroga ,  Samir Soni

Inventor： Paul Kelleher ,  Diarmuid McSwiney ,  Conor O'Keeffe ,  Emilio Quiroga ,  Samir Soni

IPC: H04L7/00

CPC classification number: H04L7/0338 ,  H04L7/042

Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Abstract translation: 无线通信设备包括多个子系统和时钟生成逻辑，其布置成生成要应用于子系统数量的至少一个时钟信号。 子系统的数量之一包括用于接收输入数据的采样逻辑，并且使用施加到采样逻辑的至少一个时钟信号的时钟周期的多个分离相位对输入数据位执行初始采样，从而产生多相分离采样 输入数据位的输出。 采样逻辑被配置为在多个中间相位的多相分离采样输出上执行多个重采样操作，从而在执行多相分离中间采样输出的最终采样之前产生多相分离中间采样输出 所述至少一个时钟信号的单相以产生采样的输入数据信号。