公开(公告)号：US08904251B2

公开(公告)日：2014-12-02

申请号：US13414955

申请日：2012-03-08

申请人： Eui-Seung Kim

发明人： Eui-Seung Kim

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318547

摘要： A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit.

摘要翻译： 半导体器件包括测试图案解码单元和扫描链单元。 测试模式从外部测试设备接收扫描模式，并根据扫描模式和扫描模式生成测试模式。 基于种子模式和期望模式对扫描模式进行解码。 扫描链单元基于测试图案执行逻辑运算，并将扫描模式反馈到测试图案解码单元。

公开(公告)号：US07852166B2

公开(公告)日：2010-12-14

申请号：US12288512

申请日：2008-10-21

申请人： Eui-Seung Kim

发明人： Eui-Seung Kim

IPC分类号： H03B5/24 ,  H03K3/02 ,  H03K3/023 ,  H03K3/0233 ,  H03K3/027 ,  H03K3/037 ,  H03L1/00

CPC分类号： H03K3/0231 ,  H03L7/099

摘要： A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

摘要翻译： 松弛振荡器补偿系统延迟。 张弛振荡器包括产生第一和第二电容器电压的第一和第二输入信号单元，接收参考电压和第一和第二电容器电压并产生补偿电压的延迟补偿单元。 在某些实施例中，电压产生单元将参考电压施加到延迟补偿单元，并且锁存单元存储由第一和第二输入信号单元比较的第一和第二比较信号，并将时钟信号和反相时钟信号发送到第一 以及第二输入信号单元。 第一和第二输入信号单元将第一和第二电容器电压与从延迟补偿单元发送的补偿电压进行比较。

公开(公告)号：US20100127767A1

公开(公告)日：2010-05-27

申请号：US12626138

申请日：2009-11-25

申请人： Eui Seung Kim ,  Yong Hee An ,  Jung-Chan Kim

发明人： Eui Seung Kim ,  Yong Hee An ,  Jung-Chan Kim

IPC分类号： H03K5/00

CPC分类号： H03K5/1252 ,  G06F21/755 ,  G06F21/77 ,  H03K5/19

摘要： An integrated circuit (IC) device is provided. The IC device includes a detector configured to detect an abnormal condition of the IC device and to generate a detection result as an attack signal, and a noise filter configured to filter out the attack signal as noise and to generate a filtered attack signal. The noise filter is configured to filter out the attack signal as noise when the attack signal is not maintained at a first logic level for a reference period and to generate the filtered attack signal when the attack signal is maintained at the first logic level for the reference period.

摘要翻译： 提供集成电路（IC）装置。 IC器件包括检测器，其被配置为检测IC器件的异常状况并产生作为攻击信号的检测结果，以及噪声滤波器，其被配置为滤除攻击信号作为噪声并产生滤波的攻击信号。 噪声滤波器被配置为当攻击信号在一个参考周期内不被保持在第一逻辑电平时，作为噪声滤除攻击信号，并且当攻击信号保持在第一逻辑电平以产生参考时产生滤波的攻击信号 期。

公开(公告)号：US20090194598A1

公开(公告)日：2009-08-06

申请号：US12353364

申请日：2009-01-14

申请人： Eui-Seung Kim ,  Jong-Cheol Kim

发明人： Eui-Seung Kim ,  Jong-Cheol Kim

IPC分类号： G06K19/067

CPC分类号： G06K19/073

摘要： A smart card system having: a smart card including a security logic circuit to detect an external attack; and a reader communicating with the smart card. The security logic circuit detects the external attack by measuring the external input capacitance through an input/output pad of the smart card and comparing the external input capacitance to the input capacitance of the reader. This improves the security of the smart card system.

摘要翻译： 一种智能卡系统，具有：智能卡，其包括用于检测外部攻击的安全逻辑电路; 以及与智能卡通信的读取器。 安全逻辑电路通过智能卡的输入/输出焊盘测量外部输入电容并将外部输入电容与读取器的输入电容进行比较来检测外部攻击。 这提高了智能卡系统的安全性。

公开(公告)号：US07483328B2

公开(公告)日：2009-01-27

申请号：US11434933

申请日：2006-05-17

申请人： Eui-Seung Kim ,  Jung-Hyun Kim

发明人： Eui-Seung Kim ,  Jung-Hyun Kim

IPC分类号： G11C5/01

CPC分类号： G11C7/1051 ,  G11C7/02 ,  G11C7/06 ,  G11C7/1063 ,  G11C29/026

摘要： Voltage glitch detection circuits and methods thereof. The voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data in response to an operation control signal and outputting data based on the reference data, a data storage circuit including at least one latch to store the reference data and a comparator circuit receiving and comparing the data output from the monitoring sense amplifier and the stored reference data from the data storage circuit, and outputting a detection signal based on the comparison. The voltage glitch detection circuit may include a first storage unit configured to latch a first voltage, a second storage unit configured to latch a second voltage, a first comparator circuit first comparing the latched first voltage with a first reference voltage and outputting a first comparison result, a second compariator circuit second comparing the second voltage with a second reference voltage and outputting a second comparison result and a third comparator circuit third comparing the first and second comparison results and outputting a reset detection signal based on the third comparison.

摘要翻译： 电压毛刺检测电路及其方法。 电压毛刺检测电路可以包括监视存储器阵列，其包括存储参考数据的至少一个存储器单元，监视读出放大器，接收来自监视存储器阵列的存储的参考数据，响应于操作控制信号放大所接收的存储的参考数据并输出 基于参考数据的数据的数据存储电路，包括用于存储参考数据的至少一个锁存器的数据存储电路;以及比较器电路，接收和比较来自监视读出放大器的数据和来自数据存储电路的存储的参考数据， 检测信号基于比较。 电压毛刺检测电路可以包括被配置为锁存第一电压的第一存储单元，被配置为锁存第二电压的第二存储单元，第一比较器电路，首先将锁存的第一电压与第一参考电压进行比较，并输出第一比较结果 第二比较器电路，其将所述第二电压与第二参考电压进行比较，并输出第二比较结果;以及第三比较器电路，其对所述第一和第二比较结果进行比较，并输出基于所述第三比较的复位检测信号。

公开(公告)号：US07085979B2

公开(公告)日：2006-08-01

申请号：US10443427

申请日：2003-05-22

申请人： Chan-Yong Kim ,  Sang-Joo Jun ,  Eui-Seung Kim

发明人： Chan-Yong Kim ,  Sang-Joo Jun ,  Eui-Seung Kim

IPC分类号： G01R31/28

CPC分类号： G11C16/225 ,  G06K19/073 ,  G06K19/07363 ,  G11C5/143

摘要： A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

公开(公告)号：US20120166901A1

公开(公告)日：2012-06-28

申请号：US13242600

申请日：2011-09-23

申请人： Eui Seung Kim

发明人： Eui Seung Kim

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318555

摘要： An integrated circuit (IC) is provided. The IC includes a scan controller and a target logic circuit configured to receive a scan input pattern in response to a control of the scan controller, to execute an operation according to the scan input pattern, and to output an execution result. The scan controller compares the execution result with a scan output pattern and outputs a comparison result. The IC can perform a scan test on a particular block that is not controlled by a CPU in a smart card without an additional pad.

摘要翻译： 提供集成电路（IC）。 IC包括扫描控制器和目标逻辑电路，其被配置为响应于扫描控制器的控制而接收扫描输入模式，以执行根据扫描输入模式的操作，并输出执行结果。 扫描控制器将执行结果与扫描输出模式进行比较，并输出比较结果。 IC可以对没有附加垫的智能卡中没有由CPU控制的特定块执行扫描测试。

公开(公告)号：US08104690B2

公开(公告)日：2012-01-31

申请号：US12353364

申请日：2009-01-14

申请人： Eui-Seung Kim ,  Jong-Cheol Kim

发明人： Eui-Seung Kim ,  Jong-Cheol Kim

IPC分类号： G06K19/06

CPC分类号： G06K19/073

摘要： A smart card system having: a smart card including a security logic circuit to detect an external attack; and a reader communicating with the smart card. The security logic circuit detects the external attack by measuring the external input capacitance through an input/output pad of the smart card and comparing the external input capacitance to the input capacitance of the reader. This improves the security of the smart card system.

摘要翻译： 一种智能卡系统，具有：智能卡，其包括用于检测外部攻击的安全逻辑电路; 以及与智能卡通信的读取器。 安全逻辑电路通过智能卡的输入/输出焊盘测量外部输入电容并将外部输入电容与读取器的输入电容进行比较来检测外部攻击。 这提高了智能卡系统的安全性。

公开(公告)号：US20090108948A1

公开(公告)日：2009-04-30

申请号：US12288512

申请日：2008-10-21

申请人： Eui-Seung Kim

发明人： Eui-Seung Kim

IPC分类号： H03K3/02

CPC分类号： H03K3/0231 ,  H03L7/099

摘要： A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

摘要翻译： 松弛振荡器补偿系统延迟。 张弛振荡器包括产生第一和第二电容器电压的第一和第二输入信号单元，接收参考电压和第一和第二电容器电压并产生补偿电压的延迟补偿单元。 在某些实施例中，电压产生单元将参考电压施加到延迟补偿单元，并且锁存单元存储由第一和第二输入信号单元比较的第一和第二比较信号，并将时钟信号和反相时钟信号发送到第一 和第二输入信号单元。 第一和第二输入信号单元将第一和第二电容器电压与从延迟补偿单元发送的补偿电压进行比较。

公开(公告)号：US20080047025A1

公开(公告)日：2008-02-21

申请号：US11606600

申请日：2006-11-30

申请人： Eui-Seung Kim

发明人： Eui-Seung Kim

IPC分类号： G06F11/00 ,  H04L9/32 ,  G08B13/14

CPC分类号： G06F21/77 ,  G06F21/554

摘要： A security apparatus within a smart card includes a plurality of security blocks with at least one shared component. Each security block that when activated generates a respective output signal indicating whether a respective detected parameter is within a respective acceptable range. A selecting unit couples the shared component to the activated one of the security blocks for minimized area and cost of the security apparatus.

摘要翻译： 智能卡内的安全装置包括具有至少一个共享组件的多个安全块。 当激活时，每个安全块产生相应的输出信号，指示相应的检测参数是否在相应的可接受范围内。 选择单元将共享组件耦合到激活的安全块中的一个，以最小化安全设备的面积和成本。