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公开(公告)号：US4783735A
公开(公告)日：1988-11-08
申请号：US810945
申请日：1985-12-19
CPC分类号： G06F12/123
摘要： A least recently used replacement level generator is constructed to include n number of register stages connected in tandem. A comparison circuit associated with each stage except the last stage compare the contents of that stage with an input level value which is to be loaded into the input stage. In the absence of an identical comparison, each stage generates a shift enable signal which is passed on to the next succeeding stage. An identical comparison inhibits the generation of the shift enable signal. Therefore, when a clock signal is applied to the device, register stages, in the presence of a control signal, cause the input level to be loaded into the input stage while the level contents of the register stages are simultaneously shifted through successive stages including the register stage whose contents are identical to the input level under the control of the shift enable signal. The contents of the output register stage accurately and instantaneously defines the least recently used replacement level for use by a cache memory.
摘要翻译： 构造最少最近使用的替换电平发生器以包括串联连接的n个寄存器级。 与除最后阶段之外的每个阶段相关联的比较电路将该级的内容与要加载到输入级的输入电平值进行比较。 在没有相同的比较的情况下，每个级产生一个传递到下一个后级的移位使能信号。 相同的比较抑制了移位使能信号的产生。 因此，当时钟信号被施加到器件时，在存在控制信号的情况下，寄存器级使得输入电平被加载到输入级，同时寄存器级的电平内容同时被移位到包括 其寄存器级的内容与在移位使能信号的控制下的输入电平相同。 输出寄存器级的内容准确和瞬时地定义了由缓存存储器使用的最近最少使用的替换级别。
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2.发明授权
公开(公告)号：US5117491A
公开(公告)日：1992-05-26
申请号：US332258
申请日：1989-03-31
IPC分类号： G06F12/14
CPC分类号： G06F12/1491
摘要： During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.
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公开(公告)号：US5134706A
公开(公告)日：1992-07-28
申请号：US511873
申请日：1990-04-19
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged. Using this information circuits in the bus interface interrupt arrangement are operated to pass data and addresses between the primary bus and the chosen bus. These circuits are operated in a manner to pass data between busses having different data path sizes.
摘要翻译： 公开了一种总线接口中断装置，其为多总线计算机系统中的每个总线提供单独的中断控制器，其中处理器连接到总线中的一个。 与处理器连接的主总线以外的每个总线决定的中断请求与连接到主总线的电路的中断一起输入到主总线的中断控制器。 中断控制器为主总线决定的中断请求连接到处理器的中断输入。 所有中断控制器连接到主总线，并可由处理器访问。 当处理器选择来自其他总线以外的总线的中断时，处理器必须读取中断控制器以首先确定哪个总线，然后识别产生已被确认的中断的电路。 在总线接口中断布置中使用这些信息电路可以在主总线和所选总线之间传递数据和地址。 这些电路的操作方式是在具有不同数据路径尺寸的总线之间传递数据。
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4.发明授权Apparatus and method for address translation of non-aligned double word virtual addresses 失效用于非对齐双字虚拟地址的地址转换的装置和方法
公开(公告)号：US5051894A
公开(公告)日：1991-09-24
申请号：US294528
申请日：1989-01-05
CPC分类号： G06F12/0886 , G06F12/10 , G06F12/1491 , G06F2212/655
摘要： In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.
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5.发明授权Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page 失效使用页面级数生成CAM的虚拟缓存系统来访问用于处理与页面相关的请求的其他存储器
公开(公告)号：US4785398A
公开(公告)日：1988-11-15
申请号：US811044
申请日：1985-12-19
CPC分类号： G06F12/0882 , G06F12/0831 , G06F12/1063
摘要： A multiprocessor computer system includes a main memory and a plurality of central processing units (CPU's) which are connected to share main memory via a common bus network. Each CPU has instruction and data cache units, each organized on a page basis for complete operating compatibility with user processes. Each cache unit includes a number of content addressable memories (CAM's) and directly addressable memories (RAM's) organized to combine associative and direct mapping of data or instructions on a page basis. An input CAM in response to a CPU address provides a cache address which includes a page level number for identifying where all of the required information resides in the other memories for processing requests relating to the page. This organization permits the processing of either virtual or physical addresses with improved speed and reduced complexity and the ability to detect and eliminate both consistency and synonym problems.
摘要翻译： 多处理器计算机系统包括主存储器和多个中央处理单元（CPU），其经由公共总线网络连接以共享主存储器。 每个CPU都有指令和数据缓存单元，每个单元都以页面为单位进行组织，以便与用户进程完全兼容。 每个高速缓存单元包括多个内容可寻址存储器（CAM）和可直接寻址的存储器（RAM），其被组织以组合以组合基于页面的数据或指令的关联和直接映射。 响应于CPU地址的输入CAM提供缓存地址，该缓存地址包括用于识别所有所需信息驻留在其他存储器中的页面级别号码，用于处理与该页面有关的请求。 该组织允许以改进的速度和降低的复杂性处理虚拟或物理地址，并且能够检测和消除一致性和同义词问题。
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公开(公告)号：US5125085A
公开(公告)日：1992-06-23
申请号：US402192
申请日：1989-09-01
申请人： Forrest M. Phillips
发明人： Forrest M. Phillips
IPC分类号： G06F12/12
CPC分类号： G06F12/123
摘要： A virtual memory management cache memory system has a plurality of directory and buffer store levels for storing page descriptor information. The cache memory directories and a least recently used (LRU) apparatus for replacing information within the buffer store on a least recently used basis are constructed from the same type of standard cache address directory part. Programmable control circuits generate the required input data and control signals which are applied to the LRU apparatus for obtaining signals which indicate a next level to be replaced on a least recently used basis and for updating the contents of the LRU apparatus on a most recently used basis.
摘要翻译： 虚拟存储器管理高速缓冲存储器系统具有用于存储页面描述符信息的多个目录和缓冲存储级别。 从相同类型的标准高速缓存地址目录部分构建高速缓存存储器目录和用于在最近最少使用的基础上替换缓冲存储器内的信息的最近最少使用的（LRU）装置。 可编程控制电路产生所需的输入数据和控制信号，这些输入数据和控制信号被施加到LRU装置，用于获得指示将在最近使用的基础上被替换的下一个级别的信号，并且用于在最近使用的基础上更新LRU装置的内容 。
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