公开(公告)号：US4017802A

公开(公告)日：1977-04-12

申请号：US596624

申请日：1975-07-17

申请人： Francesco Ferrarin

发明人： Francesco Ferrarin

IPC分类号： G05B19/045 ,  H03K3/78 ,  H03K5/15 ,  H03K17/02 ,  H03K13/247

CPC分类号： H03K3/78 ,  G05B19/045 ,  H03K5/1502

摘要： A stored electronic device for producing pulses having predetermined rate and sequence on a number of output channels with a single input for supply and start. A selector is provided for preselecting the number of pulses which at each operation of the device are made sequentially available in the respective output channel or channels; two logical gates are energized by the operation of the device, performing the function of setting to zero all of the bistable logics and blocking a decoder. A fast oscillator acts upon a first counter capable of supplying scanning sequences to the decoder, and one or more buffer power stages with a memory or storage which is independent of any interruption of the power supply, the inputs of which are connected to the decoder and the outputs of which form the device output channels; the memory in the buffer stages being capable of blocking the fast oscillator and releasing a slow oscillator. A second counter supplies respective signals to logical gates for selection of the pulse sequences, energizing that logical gate which has been preselected by the selector; an inverter or changeover switch receives a signal from the energized logical gate producing a pulse which will block the slow oscillator determining the pulse sequence; and a resetting circuit is energized to bring the memory to its initial state.

摘要翻译： 一种存储的电子设备，用于产生具有预定速率和序列的脉冲，其具有用于供应和启动的单个输入的多个输出通道。 提供一个选择器，用于预先选择在相应的输出通道或通道中使设备的每个操作顺序可用的脉冲数; 两个逻辑门由器件的操作激励，执行将所有双稳态逻辑设置为零并阻塞解码器的功能。 快速振荡器作用于能够向解码器提供扫描序列的第一计数器，以及具有存储器或存储器的一个或多个缓冲功率级，其独立于电源的任何中断，其输入连接到解码器， 其输出形成设备输出通道; 缓冲级中的存储器能够阻挡快速振荡器并释放慢振荡器。 第二计数器将各个信号提供给用于选择脉冲序列的逻辑门，激励由选择器预先选择的逻辑门; 逆变器或转换开关接收来自通电逻辑门的信号，产生将阻止慢振荡器确定脉冲序列的脉冲; 并且复位电路被通电以使存储器处于其初始状态。