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8 条记录 (耗时 0.008 秒)

    Addressing circuit
    2.
    发明授权
    Addressing circuit 失效
    寻址电路

    公开(公告)号：US3576434A

    公开(公告)日：1971-04-27

    申请号：US3576434D

    申请日：1968-02-23

    申请人： TELETYPE CORP

    发明人： RESZKA ALFONS

    IPC分类号： G11C17/02 ,  H03K13/247

    CPC分类号： G11C17/02

    摘要： A transformer-coupled memory addressing circuit uses first and second groups of addressing transformers with each addressing input being applied to the primary winding of one of the transformers of the first group and all but one of the primary windings of the second group. Each primary winding of each transformer of the first group links a plurality of secondary windings equal in number to the number of transformers in the second group. Each of these secondaries of the first group then is connected in series with an oppositely-wound secondary from a different transformer in the second group, so that only when a secondary winding of the first group has current induced in it in the absence of current induced in its series-connected winding of the second group is the desired output obtained for a particular address.

    Decimal-binary code conversion system
    4.
    发明授权
    Decimal-binary code conversion system 失效
    十二进制代码转换系统

    公开(公告)号：US3731074A

    公开(公告)日：1973-05-01

    申请号：US3731074D

    申请日：1971-03-12

    申请人： DENKI ONKYO CO LTD

    发明人： MASUDA N

    IPC分类号： H03M7/04 ,  H03K17/90 ,  H03M7/08 ,  H03M7/12 ,  G06F5/02 ,  H03K13/24 ,  H03K13/247

    CPC分类号： H03M7/12 ,  H03K17/90 ,  H03M7/08

    摘要： A decimal-binary code conversion system wherein four amplifying circuits are formed by respectively connecting four magnetroresistance effect devices formed as a bridge circuit to each of four amplifiers which produce different output signals, four different numerical values being binary-coded with independent operation of four amplifying circuits, and six numerical values being binary-coded with composite operations of the two of four amplifying circuits.

    摘要翻译： 一个十进制二进制代码转换系统，其中四个放大电路是通过将形成为桥接电路的四个磁阻效应器件分别连接到产生不同输出信号的四个放大器中的每一个形成的，四个不同的数值被二进制编码， 四个放大电路，六个数值由四个放大电路中的两个的复合操作进行二进制编码。

    Stored electronic device for producing pulses having predetermined rate and sequence
    6.
    发明授权
    Stored electronic device for producing pulses having predetermined rate and sequence 失效
    存储用于产生具有预定速率和顺序的脉冲的电子设备

    公开(公告)号：US4017802A

    公开(公告)日：1977-04-12

    申请号：US596624

    申请日：1975-07-17

    申请人： Francesco Ferrarin

    发明人： Francesco Ferrarin

    IPC分类号： G05B19/045 ,  H03K3/78 ,  H03K5/15 ,  H03K17/02 ,  H03K13/247

    CPC分类号： H03K3/78 ,  G05B19/045 ,  H03K5/1502

    摘要： A stored electronic device for producing pulses having predetermined rate and sequence on a number of output channels with a single input for supply and start. A selector is provided for preselecting the number of pulses which at each operation of the device are made sequentially available in the respective output channel or channels; two logical gates are energized by the operation of the device, performing the function of setting to zero all of the bistable logics and blocking a decoder. A fast oscillator acts upon a first counter capable of supplying scanning sequences to the decoder, and one or more buffer power stages with a memory or storage which is independent of any interruption of the power supply, the inputs of which are connected to the decoder and the outputs of which form the device output channels; the memory in the buffer stages being capable of blocking the fast oscillator and releasing a slow oscillator. A second counter supplies respective signals to logical gates for selection of the pulse sequences, energizing that logical gate which has been preselected by the selector; an inverter or changeover switch receives a signal from the energized logical gate producing a pulse which will block the slow oscillator determining the pulse sequence; and a resetting circuit is energized to bring the memory to its initial state.

    摘要翻译： 一种存储的电子设备，用于产生具有预定速率和序列的脉冲，其具有用于供应和启动的单个输入的多个输出通道。 提供一个选择器，用于预先选择在相应的输出通道或通道中使设备的每个操作顺序可用的脉冲数; 两个逻辑门由器件的操作激励，执行将所有双稳态逻辑设置为零并阻塞解码器的功能。 快速振荡器作用于能够向解码器提供扫描序列的第一计数器，以及具有存储器或存储器的一个或多个缓冲功率级，其独立于电源的任何中断，其输入连接到解码器， 其输出形成设备输出通道; 缓冲级中的存储器能够阻挡快速振荡器并释放慢振荡器。 第二计数器将各个信号提供给用于选择脉冲序列的逻辑门，激励由选择器预先选择的逻辑门; 逆变器或转换开关接收来自通电逻辑门的信号，产生将阻止慢振荡器确定脉冲序列的脉冲; 并且复位电路被通电以使存储器处于其初始状态。

    Digital-analog converting apparatus
    7.
    发明授权
    Digital-analog converting apparatus 失效
    数字模拟转换设备

    公开(公告)号：US3688301A

    公开(公告)日：1972-08-29

    申请号：US3688301D

    申请日：1970-10-13

    申请人： TAKEDA RIKEN IND CO LTD

    发明人： SUZUKI TAKASHI ,  FURUKAWA HIKARU

    IPC分类号： H03M1/00 ,  H03K13/247

    CPC分类号： H03M1/72

    摘要： This invention relates to a digital-analogue converting apparatus wherein an input winding in which the number of turns can be varied, an output winding, and a magnetic flux detecting winding are wound on a magnetic core. The input winding is connected with a constant current source through means for selecting the number of input turns according to a digital progression, and the output winding is connected with a variable current source through a standard resistance so that a direct current voltage corresponding to only the number of input turns representing a digital quantity may be obtained as output.

    摘要翻译： 本发明涉及数字模拟转换装置，其中可以改变匝数的输入绕组，输出绕组和磁通量检测绕组缠绕在磁芯上。 输入绕组通过用于根据数字进位选择输入匝数的装置与恒定电流源连接，并且输出绕组通过标准电阻与可变电流源连接，使得仅对应于 可以获得表示数字量的输入匝数作为输出。