公开(公告)号：US20070130246A1

公开(公告)日：2007-06-07

申请号：US11699737

申请日：2007-01-29

申请人： Onchuen (Daryn) Lau ,  Matthew Ornes ,  Chris Bergen ,  Robert Divivier ,  Gene Chui ,  Christopher Norrie ,  King-Shing (Frank) Chui

发明人： Onchuen (Daryn) Lau ,  Matthew Ornes ,  Chris Bergen ,  Robert Divivier ,  Gene Chui ,  Christopher Norrie ,  King-Shing (Frank) Chui

IPC分类号： G06F15/16

CPC分类号： G06F1/14 ,  H04L2012/5674

摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

摘要翻译： 在具有独立时钟的作业执行电路（例如，有效载荷处理器）和独立时钟的作业排序电路（例如，请求和有效载荷供应商）的系统中，提供协调机制以协调独立时钟的电路之间的交换。 协调机制包括使用传输的时间戳来调度所请求作业的作业执行电路内的无竞争性能的那些机制。 协调机构附加地或备选地包括静态和动态速率限制装置，其被配置为防止更快时钟的一个独立时钟的电路压倒更独立时钟的电路中更慢时钟的其他电路。 在一个实现中，独立时钟的电信货架容纳一组分布式的线卡和交换卡。 在独立时钟的架之间提供异步互连，用于在分布式线路卡和分布式交换卡之间传送作业请求和有效载荷数据。 多架系统是可扩展的和可靠的，因为可以根据需要将额外的或更换的线路和交换机卡插入独立时钟的架子中的一个或另一个，并且因为不需要统一的时钟树来同步互连的活动，而是 独立时钟的货架。

公开(公告)号：US06898211B1

公开(公告)日：2005-05-24

申请号：US09334693

申请日：1999-06-16

申请人： Onchuen D. Lau ,  Frank Chui ,  Gene Chui ,  Gary Kipnis ,  Gurmohan Samrao ,  Neil King

发明人： Onchuen D. Lau ,  Frank Chui ,  Gene Chui ,  Gary Kipnis ,  Gurmohan Samrao ,  Neil King

IPC分类号： H04J3/06

CPC分类号： H04J3/0697

摘要： A synchronization state for a local clock generating circuit of a first of a number of components of a distributed system is maintained according to a number of local clock cycles recorded between successive occurrences of a global synchronization signal provided to the components within the distributed system. The local clock generating circuit may enters the synchronization state only after observing a predetermined number of occurrences of successive local clock cycles between instances of the global synchronization signal. The local clock generating circuit continues to provide local control signals for the first of the components at time instants corresponding to the number of local clock cycles even after an instance of the global synchronization signal is observed at a time instant corresponding to one local clock cycle more or less than the number of local clock cycles. However, the local clock generating circuit enters an alarm state when the global synchronization signal is observed at time instants corresponding to more than one local clock cycle more or less than the number of local clock cycles.

摘要翻译： 根据在分布式系统中提供给组件的全局同步信号的连续出现之间记录的本地时钟周期的数量来保持分布式系统的多个组件中的第一个组件的本地时钟发生电路的同步状态。 本地时钟发生电路只有在观察到全局同步信号的实例之间的连续本地时钟周期的预定次数的出现之后，才能进入同步状态。 本地时钟发生电路继续在对应于本地时钟周期的数量的时刻在第一个分量提供本地控制信号，即使在对应于一个本地时钟周期的时间点观察到全局同步信号的一个实例之后 或小于本地时钟周期的数量。 然而，当在多于或多于本地时钟周期的多于一个本地时钟周期的时刻观察全局同步信号时，本地时钟发生电路进入报警状态。

公开(公告)号：US06628608B1

公开(公告)日：2003-09-30

申请号：US09277518

申请日：1999-03-26

申请人： Onchuen Lau ,  Frank Chui ,  Gene Chui ,  Gary Kipnis ,  Gurmohan Samrao

发明人： Onchuen Lau ,  Frank Chui ,  Gene Chui ,  Gary Kipnis ,  Gurmohan Samrao

IPC分类号： G01R3108

CPC分类号： H04L49/351 ,  H04L49/1523 ,  H04L49/25 ,  H04L49/30 ,  H04L49/55 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9084

摘要： A method of managing a network switch. The method having the first step of detecting a status of a set of physical ports on an interface card in the network switch. Then, determining if the status is in a first state that indicates that all physical ports in the interface card are inaccessible. If the status is in the first state, then accepting all traffic for the set of physical ports. Also disclosed is an apparatus for performing the method.

摘要翻译： 一种管理网络交换机的方法。 该方法具有检测网络交换机中的接口卡上的一组物理端口的状态的第一步骤。 然后，确定状态是否处于表示接口卡中的所有物理端口不可访问的第一状态。 如果状态处于第一状态，则接受该物理端口的所有流量。 还公开了一种用于执行该方法的装置。

公开(公告)号：US07356722B2

公开(公告)日：2008-04-08

申请号：US11699737

申请日：2007-01-29

申请人： Onchuen (Daryn) Lau ,  Matthew D. Ornes ,  Chris D. Bergen ,  Robert J. Divivier ,  Gene K. Chui ,  Christopher I. W. Norrie ,  King-Shing (Frank) Chui

发明人： Onchuen (Daryn) Lau ,  Matthew D. Ornes ,  Chris D. Bergen ,  Robert J. Divivier ,  Gene K. Chui ,  Christopher I. W. Norrie ,  King-Shing (Frank) Chui

IPC分类号： G06F1/12

CPC分类号： G06F1/14 ,  H04L2012/5674

摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

摘要翻译： 在具有独立时钟的作业执行电路（例如，有效载荷处理器）和独立时钟的作业排序电路（例如，请求和有效载荷供应商）的系统中，提供协调机制以协调独立时钟的电路之间的交换。 协调机制包括使用传输的时间戳来调度所请求作业的作业执行电路内的无竞争性能的那些机制。 协调机构附加地或备选地包括静态和动态速率限制装置，其被配置为防止更快时钟的一个独立时钟的电路压倒更独立时钟的电路中更慢时钟的其他电路。 在一个实现中，独立时钟的电信货架容纳一组分布式的线卡和交换卡。 在独立时钟的架之间提供异步互连，用于在分布式线路卡和分布式交换卡之间传送作业请求和有效载荷数据。 多架系统是可扩展的和可靠的，因为可以根据需要将额外的或更换的线路和交换机卡插入独立时钟的架子中的一个或另一个，并且因为不需要统一的时钟树来同步互连的活动，而是 独立时钟的货架。

公开(公告)号：US06747971B1

公开(公告)日：2004-06-08

申请号：US09295429

申请日：1999-04-20

申请人： David A. Hughes ,  Daryn Lau ,  Dan Klausmeier ,  Eugene Wang ,  Madhav Marathe ,  Frank Chui ,  Gene K. Chui ,  Gary Kipnis ,  Gurmohan S. Samrao ,  Lionel A. King

发明人： David A. Hughes ,  Daryn Lau ,  Dan Klausmeier ,  Eugene Wang ,  Madhav Marathe ,  Frank Chui ,  Gene K. Chui ,  Gary Kipnis ,  Gurmohan S. Samrao ,  Lionel A. King

IPC分类号： H04L1256

CPC分类号： H04L12/5601 ,  H04L49/153 ,  H04L49/203 ,  H04L49/255 ,  H04L49/3081 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04Q11/0478

摘要： An apparatus is described comprising an ingress port and a plurality of switch planes where each of the switch planes has a dedicated scheduler and each of the switch planes are communicatively coupled to the ingress port. The switch planes may further have at least one input control port and at least one output control port where each of the input control ports are coupled to each of the output control ports in a crossbar arrangement. The communicative coupling may further comprise one of the input control ports coupled to the ingress port. Furthermore, the ingress port may have at least one unicast queue which is dedicated to a specific egress port. The ingress port may also have a multicast queue. The dedicated scheduler may further comprise a pointer to determine priority between multicast and unicast traffic, a pointer to determine priority between contending input control ports having multicast traffic and/or a pointer for each of the output control ports to determine priority between contending input control ports having unicast traffic. The apparatus may also further comprise a plurality of ingress ports where each of the ingress ports are communicatively coupled to one of each of the input control ports.

摘要翻译： 描述了一种装置，其包括入口端口和多个开关平面，其中每个开关平面具有专用调度器，并且每个开关平面通信地耦合到入口端口。 开关平面还可以具有至少一个输入控制端口和至少一个输出控制端口，其中每个输入控制端口以交叉布置方式耦合到每个输出控制端口。 交流耦合还可以包括耦合到入口端口的输入控制端口之一。 此外，入口端口可以具有专用于特定出口端口的至少一个单播队列。 入口端口也可以具有多播队列。 专用调度器还可以包括用于确定多播和单播业务之间的优先级的指针，用于确定具有多播业务的竞争输入控制端口和/或每个输出控制端口的指针之间的优先级的指针，以确定竞争输入控制端口 具有单播流量。 该设备还可以包括多个入口端口，其中每个入口端口通信地耦合到每个输入控制端口中的一个。

公开(公告)号：US07181485B1

公开(公告)日：2007-02-20

申请号：US09997507

申请日：2001-11-26

申请人： Onchuen (Daryn) Lau ,  Matthew D. Ornes ,  Chris D. Bergen ,  Robert J. Divivier ,  Gene K. Chui ,  Christopher I. W. Norrie ,  King-Shing (Frank) Chui

发明人： Onchuen (Daryn) Lau ,  Matthew D. Ornes ,  Chris D. Bergen ,  Robert J. Divivier ,  Gene K. Chui ,  Christopher I. W. Norrie ,  King-Shing (Frank) Chui

IPC分类号： G06F15/16

CPC分类号： G06F1/14 ,  H04L2012/5674

摘要： In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves.

公开(公告)号：US07079485B1

公开(公告)日：2006-07-18

申请号：US09847711

申请日：2001-05-01

申请人： Onchuen (Daryn) Lau ,  Chris D. Bergen ,  Robert J. Divivier ,  Gene K. Chui ,  Christopher I. W. Norrie ,  Matthew D. Ornes ,  King-Shing (Frank) Chui

发明人： Onchuen (Daryn) Lau ,  Chris D. Bergen ,  Robert J. Divivier ,  Gene K. Chui ,  Christopher I. W. Norrie ,  Matthew D. Ornes ,  King-Shing (Frank) Chui

IPC分类号： H04L12/56 ,  H04J14/08

CPC分类号： H04L49/45 ,  H04L49/201 ,  H04L49/3045 ,  H04L49/357 ,  H04L49/503 ,  H04L2012/5618

摘要： A digital switching system comprises: (a) a line card layer containing a plurality of real or virtual line cards; (b) a switch card layer containing a plurality of real or virtual switch cards; and (c) an interface layer interposed between the line card layer and the switch card layer for providing serialization support services so that one or more of the line cards and switch cards can be operatively and conveniently disposed in a first shelf or on a first backplane that is spaced apart from a second shelf or from a second backplane supporting others of the line cards and/or switch cards. Such an arrangement allows for scalable expansion of the switching system in terms of number of lines served and/or transmission rates served. The flexibility of the system is owed in part to payload data being carried within payload-carrying regions of so-called ZCell signals as the payload data moves between the line card layer and the switch fabric layer.

摘要翻译： 数字交换系统包括：（a）包含多个真实或虚拟线路卡的线路卡层; （b）包含多个实际或虚拟交换卡的交换机卡层; 以及（c）插入在线卡层和开关卡层之间的界面层，用于提供串行化支持服务，使得线卡和开关卡中的一个或多个可以可操作地和方便地设置在第一架或第一背板 其与第二搁架间隔开，或者从支撑其他线路卡和/或开关卡的第二背板间隔开。 这样的布置允许在服务的线路数量和/或传输速率方面可以扩展交换系统。 当有效载荷数据在线路卡层和交换结构层之间移动时，系统的灵活性部分归因于在所谓的ZCell信号的有效负载区域内承载的有效载荷数据。

公开(公告)号：US06578092B1

公开(公告)日：2003-06-10

申请号：US09295680

申请日：1999-04-21

申请人： O. Daryn Lau ,  Frank Chui ,  Gene Chui ,  Gary Kipnis ,  Gurmobau Samrao ,  Neil King

发明人： O. Daryn Lau ,  Frank Chui ,  Gene Chui ,  Gary Kipnis ,  Gurmobau Samrao ,  Neil King

IPC分类号： G06F1300

CPC分类号： H04L25/14 ,  H04L7/005

摘要： A communication interface is described to align at a destination data transmitted through different channels before that data is read out. The communication interface includes a receiver circuit that has a plurality of buffers. Each buffer is coupled to a corresponding channel to receive data therethrough. The communication interface also includes a control circuit, coupled to the plurality of buffers, to enable reading of data from the plurality of buffers when each of the plurality of buffers has received at least one unit of data.

摘要翻译： 描述通信接口以在读出该数据之前通过不同信道发送的目的地数据进行对齐。 通信接口包括具有多个缓冲器的接收器电路。 每个缓冲器耦合到相应的通道以接收数据。 通信接口还包括耦合到多个缓冲器的控制电路，以便当多个缓冲器中的每一个已经接收到至少一个数据单元时，能够从多个缓冲器读取数据。