公开(公告)号：US06737326B2

公开(公告)日：2004-05-18

申请号：US09852921

申请日：2001-05-10

申请人： Philipp Steinmann ,  Stuart M. Jacobsen ,  Louis N. Hutter ,  Fred D. Bailey

发明人： Philipp Steinmann ,  Stuart M. Jacobsen ,  Louis N. Hutter ,  Fred D. Bailey

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L21/32051 ,  H01L23/522 ,  H01L27/0802 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.

摘要翻译： 一种用于将薄膜电阻器集成到互连工艺流程中的方法，其中一个金属层用作硬掩模。 在通孔（42）蚀刻和填充之后，沉积薄膜电阻器材料（62）。 然后沉积金属互连层（76），包括所需的任何阻挡层。 然后将金属引线（70）与薄膜电阻器（60）的形状一起蚀刻。 然后去除薄膜电阻器（60）上方的金属（76）。

公开(公告)号：US06645821B2

公开(公告)日：2003-11-11

申请号：US10102290

申请日：2002-03-20

申请人： Fred D. Bailey ,  Stuart M. Jacobsen

发明人： Fred D. Bailey ,  Stuart M. Jacobsen

IPC分类号： H01L2120

CPC分类号： H01L23/5228 ,  H01L21/28044 ,  H01L21/28114 ,  H01L27/016 ,  H01L28/20 ,  H01L29/42376 ,  H01L29/4941 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.

公开(公告)号：US06921962B1

公开(公告)日：2005-07-26

申请号：US09452691

申请日：1999-12-02

申请人： Fred D. Bailey ,  Stuart M. Jacobsen

发明人： Fred D. Bailey ,  Stuart M. Jacobsen

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L23/522 ,  H01L27/01 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L23/62 ,  H01L27/102 ,  H01L29/00 ,  H01L31/111

CPC分类号： H01L23/5228 ,  H01L21/28044 ,  H01L21/28114 ,  H01L27/016 ,  H01L28/20 ,  H01L29/42376 ,  H01L29/4941 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.

摘要翻译： 薄膜电阻（60）包含在集成电路的两个金属互连层（40,100）之间。 可以通过通孔（95）从电阻器（60）上方的金属层（100）到薄膜电阻器（60）和下面的金属层（40）同时进行接触。 电阻器（60）可以包括通孔（95）下面的硬掩模（70）的部分，以在通孔（95）蚀刻期间保护电阻材料（60）。 这种设计提供了制造电阻器（60）的灵活性，因为工艺，材料和化学品不必同时满足电阻器（60）和集成电路的其余部分（特别是互连层40）的条件。

公开(公告)号：US06326256B1

公开(公告)日：2001-12-04

申请号：US09406457

申请日：1999-09-27

申请人： Fred D. Bailey ,  Stuart M. Jacobsen

发明人： Fred D. Bailey ,  Stuart M. Jacobsen

IPC分类号： H01L218234

CPC分类号： H01L21/76894 ,  H01L28/20 ,  H01L28/24

摘要： A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total thickness of the dielectric stack (60) between the silicon substrate and the top of the dielectric stack just prior to the formation of the thin film resistor (80). Then, the thickness of the dielectric stack (60) is adjusted (60+70) to be an odd integer number of laser quarter wavelengths. The thin film resistor (60) is then formed and overlying dielectric (120) is deposited. The thickness of the overlying dielectric (120) may likewise be adjusted (120+130) to be an odd integer number of laser quarter wavelengths.

摘要翻译： 薄膜电阻器处理流程解决了在优化的多层堆叠（60,70）中精确地并入要修整的电阻器（80）的问题。 这通过在形成薄膜电阻器（80）之前测量硅衬底和电介质叠层的顶部之间的电介质叠层（60）的总厚度来实现。 然后，将电介质堆叠（60）的厚度调整为（60 + 70）为激光四分之一波长的奇数整数。 然后形成薄膜电阻器（60），并沉积上覆电介质（120）。 上覆电介质（120）的厚度同样可以被调节（120 + 130），成为激光四分之一波长的奇数整数。