ROBUST TESTING FOR DISCRETE-TIME AND CONTINUOUS-TIME SYSTEM MODELS
    3.
    发明申请
    ROBUST TESTING FOR DISCRETE-TIME AND CONTINUOUS-TIME SYSTEM MODELS 审中-公开
    用于分离和连续系统模型的鲁棒测试

    公开(公告)号:US20100299651A1

    公开(公告)日:2010-11-25

    申请号:US12708651

    申请日:2010-02-19

    CPC classification number: G06F17/5036 G06F8/30 G06F11/362 G06F2217/16

    Abstract: A system and method for testing robustness of a simulation model of a cyber-physical system includes computing a set of symbolic simulation traces for a simulation model for a continuous time system stored in memory, based on a discrete time simulation of given test inputs stored in memory. Simulation errors are accounted for due to at least one of numerical instabilities and numeric computations. The set of symbolic simulation traces are validated with respect to validation properties in the simulation model. Portions of the simulation model description are identified that are sources of the simulation errors.

    Abstract translation: 用于测试网络物理系统的仿真模型的鲁棒性的系统和方法包括基于存储在存储器中的给定测试输入的离散时间模拟来计算用于存储在存储器中的连续时间系统的模拟模型的一组符号仿真轨迹 记忆。 由于数值不稳定性和数值计算中的至少一个,造成了模拟误差。 关于仿真模型中的验证属性验证了一组符号仿真轨迹。 识别模拟模型描述的部分是模拟错误的来源。

    Automated test generation for structural coverage for temporal logic falsification of cyber-physical systems

    公开(公告)号:US10409706B2

    公开(公告)日:2019-09-10

    申请号:US15721243

    申请日:2017-09-29

    Abstract: One embodiment is a methodology for model verification. An embodiment obtaining, by a processor, a model for a system; identifying, by the processor, at least one block within the model that has a branching structure; identifying, by the processor, at least one model variable affecting a switching condition of the identified at least one block; generating, by the processor, an extended finite state machine modeling a switching behavior of the identified at least one block by using the at least one model variable; combining, by the processor, at least one output variable of the extended finite state machine with at least one of a first output port and a second output port of the system included in the model; and performing, by the processor, model verification and coverage of the model that utilizes outputs from the first output port and the second output port to verify the model.

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