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公开(公告)号：US06369616B1
公开(公告)日：2002-04-09
申请号：US09599050
申请日：2000-06-21
IPC分类号： H03K19096
CPC分类号： H03K19/1731
摘要： A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.
摘要翻译： 第一上拉晶体管具有耦合到时钟信号线的栅极和耦合到第一下拉晶体管和电压钳两者的漏极。 第二上拉晶体管具有还耦合到时钟信号线的栅极和耦合到第二下拉晶体管和电压钳两者的漏极。 共享上拉晶体管具有也耦合到时钟信号线的栅极和耦合到第一和第二下拉晶体管的漏极。 共享上拉晶体管可以用于对电路的输出节点进行预充电。 该电路可用于时钟缓冲应用。
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公开(公告)号：US6111435A
公开(公告)日：2000-08-29
申请号：US343961
申请日：1999-06-30
申请人： Jiann-Cherng James Lan , Mahadevamurty Nemani , Narsing K. Vijayrao , Wenjie Jiang , Sudarshan Kumar
发明人： Jiann-Cherng James Lan , Mahadevamurty Nemani , Narsing K. Vijayrao , Wenjie Jiang , Sudarshan Kumar
IPC分类号： H03K17/693 , H03K19/173 , H03K19/20
CPC分类号： H03K17/693 , H03K19/1731
摘要： A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.
摘要翻译： 电路包括第一和第二上拉晶体管，其分别具有分别耦合到单独的电压钳位的第一和第二漏极。 两个上拉晶体管中的每一个的栅极耦合到时钟信号线。 电路还包括共享下拉晶体管，其栅极耦合到时钟信号线。 共享下拉晶体管的漏极经由与共用下拉晶体管串联的至少一个下拉晶体管耦合到第一漏极。 共享下拉晶体管的漏极还通过与共享下拉晶体管串联的至少一个下拉晶体管耦合到第二漏极。 该电路可用于多路复用应用。
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3.发明授权
公开(公告)号：US6124737A
公开(公告)日：2000-09-26
申请号：US345972
申请日：1999-06-30
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.
摘要翻译： 时钟缓冲器包括时钟上拉晶体管和时钟控制下拉晶体管。 时钟上拉晶体管具有耦合到输出线的漏极和耦合到时钟信号线的栅极。 时钟控制的下拉晶体管包括耦合到输出线的漏极，耦合到时钟信号线的栅极并具有宽度Y.该缓冲器还包括第一下拉晶体管，其具有耦合到时钟信号源的漏极 下拉晶体管，耦合到第一输入信号线的栅极，并且具有比Y大至少10％的宽度。与较传统的时钟缓冲器相比，该时钟缓冲器提供了降低的功耗。
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公开(公告)号：US06341099B1
公开(公告)日：2002-01-22
申请号：US09672950
申请日：2000-09-29
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors. Each of the sustainer circuits may include a pair of back-to-back inverters.
摘要翻译： 一种用于降低由多个数据单元组成的数据存储设备中的功耗的技术包括将数据单元的数量排列成簇，每个簇具有多个数据单元，其数据使能输入连接在一起。 提供数据写总线以向数据单元数量的数据使能输入提供数据使能信号。 在簇和写入数据总线之间分别设置多个通过门。 通过门有选择地使允许数据使能信号从写入数据总线传递到所选择的一个或多个集群的多个数据单元的数据使能输入。 多个反相器可以分别设置在通过门数和簇之间。 多个保持器电路可以分别连接到通孔的数量。 每个通过栅极可以包括一对场效应晶体管，其可以是互补场效应晶体管。 每个维持器电路可以包括一对背对背反相器。
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公开(公告)号：US6127850A
公开(公告)日：2000-10-03
申请号：US346108
申请日：1999-06-30
IPC分类号： H03K19/173 , H03K19/096
CPC分类号： H03K19/1731
摘要： A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.
摘要翻译： 第一上拉晶体管具有耦合到时钟信号线的栅极和耦合到第一下拉晶体管和电压钳两者的漏极。 第二上拉晶体管具有也耦合到时钟信号线的栅极和耦合到第二下拉晶体管和电压钳两者的漏极。 共享下拉晶体管具有也耦合到时钟信号线的栅极和耦合到第一和第二下拉晶体管的漏极。 该电路可用于时钟缓冲应用。
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