公开(公告)号：US07493467B2

公开(公告)日：2009-02-17

申请号：US11305782

申请日：2005-12-16

申请人： Geoffrey A Gould

发明人： Geoffrey A Gould

IPC分类号： G06F12/00

CPC分类号： G06F12/0646

摘要： A memory controller receives a logical address of a data unit in a memory and scrambles the logical address according to an address scrambling scheme. The address scrambling scheme maps the logical address to time-multiplexed output of physical address pins of the memory controller. At least one of the physical address pins, which is to be mapped in a time phase in a baseline design, is to be unmapped in a corresponding time phase if a dimensional parameter of the memory changes. The logical address comprises row address bits and column address bits. All of the even row address bits may be mapped in a time phase for outputting the row address, and all of the odd row address bits may be mapped in another time phase for outputting the row address. Thus, configuration flexibility of the memory controller is improved.

摘要翻译： 存储器控制器接收存储器中的数据单元的逻辑地址，并根据地址扰频方案对逻辑地址进行加扰。 地址加扰方案将逻辑地址映射到存储器控制器的物理地址引脚的时间复用输出。 如果存储器的维度参数发生变化，则在基线设计中要映射到物理地址引脚中的至少一个将在相应的时间相位中被取消映射。 逻辑地址包括行地址位和列地址位。 所有偶数行地址位可以在用于输出行地址的时间相位中被映射，并且所有奇数行地址位可以被映射到用于输出行地址的另一个时间相位中。 因此，提高了存储器控制器的配置灵活性。

公开(公告)号：US08375189B2

公开(公告)日：2013-02-12

申请号：US11322680

申请日：2005-12-30

申请人： Shekoufeh Qawami ,  Joel T. Jorgensen ,  Geoffrey A. Gould

发明人： Shekoufeh Qawami ,  Joel T. Jorgensen ,  Geoffrey A. Gould

IPC分类号： G06F12/14

CPC分类号： G11C16/22

摘要： A method and apparatus for configuring a memory device, such as a flash memory device, is herein described. Features/functional modules of a memory device, are selectable by a manufacturer, customer, or user. Instead of a manufacturer having to complete numerous redesigns of a memory product to meet multiple customer's special needs, a single all inclusive device is manufactured and the customized features are selected/configured, by the manufacturer, or by the customer themselves. By using one time programmable (OTP) flags, the features are enabled or disabled, by the manufacturer, customer, or user, and may potentially not be altered by a user later. Moreover, after configuring a memory device, a manufacturer, customer, or end user may also lock down a configuration module to ensure the configuration itself is not later intentionally or inadvertently altered.

摘要翻译： 这里描述了用于配置诸如闪存设备的存储设备的方法和设备。 存储器件的特征/功能模块可由制造商，客户或用户选择。 制造商不得不完成许多重新设计存储器产品以满足多个客户的特殊需求，而是制造单一的全包设备，并且由制造商或客户自己选择/配置定制特征。 通过使用一次性可编程（OTP）标志，功能由制造商，客户或用户启用或禁用，稍后可能不会被用户改变。 此外，在配置存储设备之后，制造商，客户或最终用户也可以锁定配置模块，以确保配置本身不会有意或无意地被改变。

公开(公告)号：US5369754A

公开(公告)日：1994-11-29

申请号：US220811

申请日：1994-03-30

申请人： Mickey L. Fandrich ,  Chakravarthy Yarlagadda ,  Rodney R. Rozman ,  Geoffrey A. Gould

发明人： Mickey L. Fandrich ,  Chakravarthy Yarlagadda ,  Rodney R. Rozman ,  Geoffrey A. Gould

IPC分类号： G06F12/14 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G06F12/00

CPC分类号： G06F12/1425 ,  G11C16/102 ,  G11C16/22 ,  G11C7/24 ,  G06F2212/2022

摘要： A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

公开(公告)号：US5353256A

公开(公告)日：1994-10-04

申请号：US85293

申请日：1993-06-30

申请人： Mickey L. Fandrich ,  Chakravarthy Yarlagadda ,  Rodney R. Rozman ,  Geoffrey A. Gould

发明人： Mickey L. Fandrich ,  Chakravarthy Yarlagadda ,  Rodney R. Rozman ,  Geoffrey A. Gould

IPC分类号： G06F12/14 ,  G11C7/24 ,  G11C16/10 ,  G11C16/22 ,  G11C7/00

CPC分类号： G06F12/1425 ,  G11C16/102 ,  G11C16/22 ,  G11C7/24 ,  G06F2212/2022

摘要： A flash memory device having a plurality of flash array blocks and a block status register circuit containing a block status register for storing a block status for each flash array block. A flash array controller circuit in the flash memory device performs program or erase operations on the flash array blocks, and maintains the block status in each block status register. An interface circuit in the flash memory device enables read access of the block status registers over a bus.

摘要翻译： 具有多个闪存阵列块的闪速存储器件和包含用于存储每个闪存阵列块的块状态的块状态寄存器的块状态寄存器电路。 闪存器件中的闪存阵列控制器电路对闪存阵列块执行编程或擦除操作，并在每个块状态寄存器中保持块状态。 闪速存储器件中的接口电路使得能够通过总线对块状态寄存器进行读取访问。

公开(公告)号：US5592641A

公开(公告)日：1997-01-07

申请号：US85546

申请日：1993-06-30

申请人： Mickey L. Fandrich ,  Salim B. Fedel ,  Thomas C. Price ,  Richard J. Durante ,  Geoffrey A. Gould ,  Timothy W. Goodell ,  Scott M. Doyle

发明人： Mickey L. Fandrich ,  Salim B. Fedel ,  Thomas C. Price ,  Richard J. Durante ,  Geoffrey A. Gould ,  Timothy W. Goodell ,  Scott M. Doyle

IPC分类号： G11C7/24 ,  G11C16/22 ,  G06F12/14

CPC分类号： G11C16/22 ,  G11C7/24

摘要： A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.

摘要翻译： 一种用于选择性地启用和禁用对闪存设备中的闪存块的写入访问的方法和设备。 锁定命令锁定并解锁包含多个闪存块的闪存阵列中的闪存块。 块数据行解码器选择闪存块的块数据区，块状态行解码器选择闪存块的块状态区。 如果锁定命令指定锁定闪存块操作，则块状态区域中的锁定位被编程为第一逻辑状态，如果锁定命令指定释放闪存块操作，则将其锁定到第二逻辑状态。 如果写保护输入从闪存器件的写保护引脚读取，则指示写锁定被使能，并且如果与该块相对应的块状态寄存器中的块使能状态位指示该块具有写锁定， 则锁定位被读取并存储到与块相对应的块状态寄存器中的块使能状态位。 写保护输入再次从写保护引脚读取，如果写保护输入指示写锁定使能，并且如果块状态寄存器中对应于块更新的块状态寄存器位指示块 有写锁定，然后发出错误信号。