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公开(公告)号：US07464217B2
公开(公告)日：2008-12-09
申请号：US11850840
申请日：2007-09-06
IPC分类号： G06F12/00
摘要： A design structure for content addressable memory including a first array of memory cells, and a second array of memory cells. A search logic circuit is configured to prevent a discharge of the second array of memory cells when a search of the first array of memory cells finds certain data.
摘要翻译： 一种用于内容可寻址存储器的设计结构，包括存储器单元的第一阵列和存储器单元的第二阵列。 搜索逻辑电路被配置为当存储器单元的第一阵列的搜索找到某些数据时，防止存储器单元的第二阵列的放电。
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公开(公告)号：US20070291561A1
公开(公告)日：2007-12-20
申请号：US11424072
申请日：2006-06-14
申请人： Geordie M. Braceras , Harold Pilo , Fred J. Towter
发明人： Geordie M. Braceras , Harold Pilo , Fred J. Towter
IPC分类号： G11C7/06
CPC分类号： G11C7/12 , G11C7/06 , G11C11/41 , G11C11/419 , G11C29/08
摘要： The present invention provides an apparatus and method to reduce the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring Sense Amplifier Assist (SAA) circuitry. In particular, the present invention is an apparatus and method that limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.
摘要翻译： 本发明提供一种降低存储器件功率的装置和方法，特别是具有感测放大器辅助（SAA）电路的静态随机存取存储器（SRAM）阵列。 特别地，本发明是将SAA电路的实现限于不符合应用电压要求的SRAM阵列块的装置和方法。
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3.发明授权High reliability content-addressable memory using shadow content-addressable memory 有权高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存公开(公告)号：US06650561B2
公开(公告)日：2003-11-18
申请号：US10059863
申请日：2002-01-30
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content-addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译： 使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。 阴影CAM与主CAM并行写入，读取和搜索。 比较并行搜索的搜索结果，如果相同，则声明为有效。 如果搜索结果不相等，则会启动纠正措施。 高可靠性内容寻址存储器可以与或不与优先编码器一起使用。
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4.发明授权Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices 失效使用PFET接入器件的SRAM单元中小信号感测的装置和方法公开(公告)号：US07724565B2
公开(公告)日：2010-05-25
申请号：US11850992
申请日：2007-09-06
IPC分类号： G11C7/12 , G11C11/41 , G11C11/419 , G11C7/06
CPC分类号： G11C7/12 , G11C7/22 , G11C11/413 , G11C2207/005
摘要： A design structure embodied in a machine readable medium used in a design process for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.
摘要翻译： 在静态随机存取存储器（SRAM）单元的读取操作期间，在用于小信号感测的设计过程中使用的机器可读介质中的设计结构包括将一对互补读出放大器数据线耦合到相应的一对互补位线 与SRAM单元相关联，以及设置读出放大器以放大在读出放大器数据线上产生的信号，其中位线对在读出放大器设置时保持耦合到读出放大器数据线。
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5.发明授权High reliability content-addressable memory using shadow content-addressable memory 失效高可靠性内容 - 可寻址内存，使用阴影内容可寻址内存公开(公告)号：US06687144B2
公开(公告)日：2004-02-03
申请号：US10430671
申请日：2003-05-06
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A high-reliability content & addressable memory using a shadow content-addressable memory (CAM) array in parallel with a primary CAM array to increase the reliability of CAM searches. The reliability of CAM searches has been less than desired because of random environmental influences that corrupt data. The shadow CAM is written, read, and searched in parallel with the primary CAM. The search results from the parallel searches are compared and, if identical, are declared valid. If the search results are not equal, corrective action is initiated. The high-reliability content-addressable memory may be used with or without priority encoders.
摘要翻译： 使用与主CAM阵列并行的阴影内容可寻址存储器（CAM）阵列的高可靠性内容和可寻址存储器，以增加CAM搜索的可靠性。 CAM搜索的可靠性已经低于期望的，因为损坏的数据是随机的环境影响。 阴影CAM与主CAM并行写入，读取和搜索。 比较并行搜索的搜索结果，如果相同，则声明为有效。 如果搜索结果不相等，则会启动纠正措施。 高可靠性内容寻址存储器可以与或不与优先编码器一起使用。
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公开(公告)号：US06219288B1
公开(公告)日：2001-04-17
申请号：US09519392
申请日：2000-03-03
IPC分类号： G11C700
CPC分类号： G11C11/417 , G11C7/1045 , G11C7/22
摘要： A SRAM module provides programmability of AC timings such that an end user can adjust or “tweak” the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.
摘要翻译： SRAM模块提供AC定时的可编程性，使得最终用户可以调整或“调整”AC定时以最大化系统性能。 可变延迟电路被放置在信号（例如，数据信号或地址信号）和SRAM建立和保持寄存器之间的路径中，该寄存器允许用户按照选定的增量来移动建立和保持窗口。 延迟电路可以提前或延迟交流定时。 以两种方式之一选择控制延迟电路的延迟程序; 通过存储在ROM设备中并由制造商预设的默认AC定时程序，或通过由SRAM芯片上提供的JTAG状态机由用户输入的专用JTAG指令和AC编程数据。 一旦选择了最佳延迟（或提前）来优化到高速缓存系统的SRAM，该用户程序可以被永久地烧录到默认ROM中，使得此后使用最佳定时作为默认值。
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