公开(公告)号：US08504976B2

公开(公告)日：2013-08-06

申请号：US13484136

申请日：2012-05-30

申请人： Zhuyuan Liu ,  Geping Liu ,  San Wong

发明人： Zhuyuan Liu ,  Geping Liu ,  San Wong

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5054 ,  G06F2217/82

摘要： In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., αj). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.

摘要翻译： 在示例实施例中，系统从自动SSN测量系统获得在静音I / O缓冲器和PLD上的每个切换I / O缓冲器之间的互感（例如，Mij）。 该系统通过将互感乘以校正因子（例如，alphaj）来计算安静I / O缓冲器和每个开关I / O缓冲器之间的校正互感。 该系统将每个校正的互感乘以流过开关I / O缓冲器的电流的比率，以获得由开关I / O缓冲器产生的感应电压。 系统对PLD上所有开关I / O缓冲器的感应电压求和，以获得所有开关I / O缓冲器在静音I / O缓冲器中引起的总感应电压的估计。 校正因子基于台架测量，并且取决于影响每个开关I / O缓冲器的同时开关噪声的幅度。

公开(公告)号：US08825420B1

公开(公告)日：2014-09-02

申请号：US12690047

申请日：2010-01-19

申请人： Geping Liu ,  Kundan Chand ,  Zhe Li ,  Wui Hung Moo ,  Joseph Boon Hock Kho

发明人： Geping Liu ,  Kundan Chand ,  Zhe Li ,  Wui Hung Moo ,  Joseph Boon Hock Kho

IPC分类号： G01R13/00

CPC分类号： G06F17/5031 ,  G01R13/00 ,  G06F17/5036 ,  G06F2217/08 ,  G06F2217/82 ,  G06F2217/84 ,  H03K19/00346

摘要： A computer implemented method for determining a timing variation for an edge of a waveform under simultaneous switching noise (SSN) conditions is provided. The method includes characterizing an impact of mutual inductive relationships on a pin while the pin is at a quiet state and characterizing a signal edge applied to the pin. The signal edge can be characterized by the slew rate in one embodiment. A voltage change related to a curve characterizing the impact of mutual inductive relationships is identified and the voltage change is applied to a curve characterizing an impact of SSN on the signal edge. The method includes calculating a timing variation correlated to the voltage change applied to the curve characterizing the impact of SSN on the signal edge and presenting the calculated timing variation.

摘要翻译： 提供了一种用于在同时开关噪声（SSN）条件下确定波形边缘的定时变化的计算机实现方法。 该方法包括在引脚处于安静状态并表征施加到引脚的信号边缘时，表征引脚上的互感关系的影响。 信号沿可以通过一个实施例中的压摆率来表征。 识别与表征互感关系影响的曲线相关的电压变化，并且将电压变化应用于表征SSN对信号边缘的影响的曲线。 该方法包括计算与应用于表征SSN对信号边缘的影响的曲线的电压变化相关的定时变化，并呈现所计算的定时变化。

公开(公告)号：US08103469B1

公开(公告)日：2012-01-24

申请号：US11297611

申请日：2005-12-07

申请人： San Wong ,  Daniel Tun Lai Chow ,  Geping Liu

发明人： San Wong ,  Daniel Tun Lai Chow ,  Geping Liu

IPC分类号： G01R13/00 ,  G01R13/02 ,  G01R29/26

CPC分类号： G01R31/3171 ,  G01R31/31709

摘要： A method for predicting a predetermined bit error rate for an actual data transmission from a transmitter to a target receiver over an actual backplane link is disclosed. The method involves defining a simulated backplane corresponding to an actual backplane link intended to be used for data transmission between a transmitter and a target receiver. Once the simulated backplane is defined, a data transmission from the transmitter to the receiver is simulated and captured across the simulated backplane. A waveform simulation of the data transmission over the simulated backplane is then generated. The waveform simulation takes into account characteristics of the simulated backplane and the target receiver. From the waveform simulation, a total jitter for a predetermined bit error rate for the data transmission is extrapolated.

摘要翻译： 公开了一种用于预测通过实际背板链路从发射机到目标接收机的实际数据传输的预定比特误码率的方法。 该方法涉及定义对应于旨在用于发射机和目标接收机之间的数据传输的实际背板链路的模拟背板。 一旦模拟背板被定义，从模拟背板模拟和捕获从发射机到接收机的数据传输。 然后生成模拟背板上的数据传输的波形模拟。 波形仿真考虑了仿真背板和目标接收机的特性。 从波形模拟中，外推了用于数据传输的预定误码率的总抖动。

公开(公告)号：US08001508B1

公开(公告)日：2011-08-16

申请号：US11877072

申请日：2007-10-23

申请人： Nafira Daud ,  Geping Liu ,  San Wong ,  Lawrence David Smith

发明人： Nafira Daud ,  Geping Liu ,  San Wong ,  Lawrence David Smith

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5072 ,  G06F2217/40 ,  G06F2217/82

摘要： A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.

摘要翻译： 提供了一种用于优化集成电路的引脚选择的方法。 引脚位置映射到向量。 集成电路引脚之间的互感关系被捕获到矩阵中。 矩阵包含每个引脚的信号状态如何影响I / O bank中其他引脚的切换的数据。 将引脚位置和串扰矩阵组合起来，以表征引脚上串扰对引脚布置的影响。 此后，用户可以决定改变引脚布置或改变引脚的采样间隔，以避免在串扰可能影响信号完整性时对引脚进行采样。 该方法可以应用于影响信号完整性的多个同时开关噪声原因机制。 在该实施例中，通过比较每个原因机制的影响来确定来自单独量化的原因机制的最坏情况引起机制。

公开(公告)号：US20120239338A1

公开(公告)日：2012-09-20

申请号：US13484136

申请日：2012-05-30

申请人： Zhuyuan Liu ,  Geping Liu ,  San Wong

发明人： Zhuyuan Liu ,  Geping Liu ,  San Wong

IPC分类号： G06F19/00

CPC分类号： G06F17/5036 ,  G06F17/5054 ,  G06F2217/82

摘要： In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., αj). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.

摘要翻译： 在示例实施例中，系统从自动SSN测量系统获得在静音I / O缓冲器和PLD上的每个切换I / O缓冲器之间的互感（例如，Mij）。 该系统通过将互感乘以校正因子（例如，αj）来计算安静I / O缓冲器和每个开关I / O缓冲器之间的校正互感。 该系统将每个校正的互感乘以流过开关I / O缓冲器的电流的比率，以获得由开关I / O缓冲器产生的感应电压。 系统对PLD上所有开关I / O缓冲器的感应电压求和，以获得所有开关I / O缓冲器在静音I / O缓冲器中引起的总感应电压的估计。 校正因子基于台架测量，并且取决于影响每个开关I / O缓冲器的同时开关噪声的幅度。

公开(公告)号：US08214781B1

公开(公告)日：2012-07-03

申请号：US12208190

申请日：2008-09-10

申请人： Zhuyuan Liu ,  Geping Liu ,  San Wong

发明人： Zhuyuan Liu ,  Geping Liu ,  San Wong

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5054 ,  G06F2217/82

摘要： In an example embodiment, the system obtains the mutual inductance (e.g., Mij) between a quiet I/O buffer and each switching I/O buffer on a PLD from an automatic SSN measurement system. The system calculates the corrected mutual inductance between the quiet I/O buffer and each switching I/O buffer by multiplying the mutual inductance by a correction factor (e.g., αj). The system multiplies each corrected mutual inductance by the rate of current flowing through the switching I/O buffer to obtain an induced voltage resulting from the switching I/O buffer. The system sums the induced voltages for all the switching I/O buffers on the PLD to obtain an estimate of total induced voltage caused in the quiet I/O buffer by all switching I/O buffers. The correction factor is based on bench measurements and depends on the amplitude of the simultaneous switching noise affecting each switching I/O buffer.

摘要翻译： 在示例实施例中，系统从自动SSN测量系统获得在静音I / O缓冲器和PLD上的每个切换I / O缓冲器之间的互感（例如，Mij）。 该系统通过将互感乘以校正因子（例如，αj）来计算安静I / O缓冲器和每个开关I / O缓冲器之间的校正互感。 该系统将每个校正的互感乘以流过开关I / O缓冲器的电流的比率，以获得由开关I / O缓冲器产生的感应电压。 系统对PLD上所有开关I / O缓冲器的感应电压求和，以获得所有开关I / O缓冲器在静音I / O缓冲器中引起的总感应电压的估计。 校正因子基于台架测量，并且取决于影响每个开关I / O缓冲器的同时开关噪声的幅度。