公开(公告)号：US07609095B2

公开(公告)日：2009-10-27

申请号：US11122002

申请日：2005-05-05

申请人： Gerald I. Grand ,  Mark Chambers ,  Baobinh Truong

发明人： Gerald I. Grand ,  Mark Chambers ,  Baobinh Truong

IPC分类号： H03K17/00

CPC分类号： G01R31/31727

摘要： A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

摘要翻译： 用于无缝重新编程时钟频率的系统和方法包括产生CPU和双倍数据速率（DDR）时钟的锁相环（PLL）。 晶体用于产生参考时钟。 CPU时钟和参考时钟是第一多路复用器的输入，DDR时钟和参考时钟是第二个多路复用器的输入。 在正常操作中，多路复用器提供CPU和DDR时钟信号作为输出。 要重新编程时钟频率并复位PLL，（1）参考时钟信号被选择为两个复用器的输出，因此器件在内部参考时钟上运行。 多路复用切换与CPU和DDR时钟信号同步。 （2）PLL重新编程，其内部压控振荡器复位，PLL以新的所需频率重新启动。 （3）当新的PLL频率输出稳定时，多路复用器与参考时钟信号同步切换回PLL生成的CPU和DDR时钟。