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    System and method for maintaining device operation during clock signal adjustments
    1.
    发明授权
    System and method for maintaining device operation during clock signal adjustments 有权
    在时钟信号调整期间保持设备运行的系统和方法

    公开(公告)号：US07609095B2

    公开(公告)日：2009-10-27

    申请号：US11122002

    申请日：2005-05-05

    申请人： Gerald I. Grand ,  Mark Chambers ,  Baobinh Truong

    发明人： Gerald I. Grand ,  Mark Chambers ,  Baobinh Truong

    IPC分类号： H03K17/00

    CPC分类号： G01R31/31727

    摘要： A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

    摘要翻译： 用于无缝重新编程时钟频率的系统和方法包括产生CPU和双倍数据速率（DDR）时钟的锁相环（PLL）。 晶体用于产生参考时钟。 CPU时钟和参考时钟是第一多路复用器的输入，DDR时钟和参考时钟是第二个多路复用器的输入。 在正常操作中，多路复用器提供CPU和DDR时钟信号作为输出。 要重新编程时钟频率并复位PLL，（1）参考时钟信号被选择为两个复用器的输出，因此器件在内部参考时钟上运行。 多路复用切换与CPU和DDR时钟信号同步。 （2）PLL重新编程，其内部压控振荡器复位，PLL以新的所需频率重新启动。 （3）当新的PLL频率输出稳定时，多路复用器与参考时钟信号同步切换回PLL生成的CPU和DDR时钟。

    System and method for maintaining device operation during clock signal adjustments
    2.
    发明申请
    System and method for maintaining device operation during clock signal adjustments 有权
    在时钟信号调整期间保持设备运行的系统和方法

    公开(公告)号：US20050259505A1

    公开(公告)日：2005-11-24

    申请号：US11122002

    申请日：2005-05-05

    申请人： Gerald Grand ,  Mark Chambers ,  Baobinh Truong

    发明人： Gerald Grand ,  Mark Chambers ,  Baobinh Truong

    IPC分类号： G01R31/317 ,  G11C8/00

    CPC分类号： G01R31/31727

    摘要： A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

    摘要翻译： 用于无缝重新编程时钟频率的系统和方法包括产生CPU和双倍数据速率（DDR）时钟的锁相环（PLL）。 晶体用于产生参考时钟。 CPU时钟和参考时钟是第一多路复用器的输入，DDR时钟和参考时钟是第二个多路复用器的输入。 在正常操作中，多路复用器提供CPU和DDR时钟信号作为输出。 要重新编程时钟频率并复位PLL，（1）参考时钟信号被选择为两个复用器的输出，因此器件在内部参考时钟上运行。 多路复用切换与CPU和DDR时钟信号同步。 （2）PLL重新编程，其内部压控振荡器复位，PLL以新的所需频率重新启动。 （3）当新的PLL频率输出稳定时，多路复用器与参考时钟信号同步切换回PLL产生的CPU和DDR时钟。

    Frequency divider and associated methods
    4.
    发明授权
    Frequency divider and associated methods 失效
    分频器和相关方法

    公开(公告)号：US07358782B2

    公开(公告)日：2008-04-15

    申请号：US11350143

    申请日：2006-02-09

    申请人： Karapet Khanoyan ,  Mark Chambers

    发明人： Karapet Khanoyan ,  Mark Chambers

    IPC分类号： H03B19/00

    CPC分类号： H03K23/66 ,  H03K21/10 ,  H03K23/54 ,  H03L7/183

    摘要： The present invention relates to frequency dividers. The frequency divider comprises an input, a counter, a first comparator, an interconnect, and an output. The counter has a counter reset port and is configured to receive a clock signal from the input and to produce a sum signal. The first comparator is configured to receive the sum signal, to compare the sum signal to a first integer, and to produce a first comparison signal. The interconnect is configured to convey the first comparison signal from the first comparator to the counter reset port. The output coupled to the first comparator. The clock signal has a periodic waveform. The sum signal represents a first sum, which equals a number of waveforms of the clock signal received by the counter after the counter has been reset. In a first embodiment, the first integer is selectable from a set of at least three consecutive integers. In a second embodiment, a frequency of the clock signal is at least 1.5 gigahertz. A third embodiment includes the features of both the first embodiment and the second embodiment.

    摘要翻译： 本发明涉及分频器。 分频器包括输入，计数器，第一比较器，互连和输出。 计数器具有计数器复位端口，并且被配置为从输入接收时钟信号并产生和信号。 第一比较器被配置为接收和信号，以将和信号与第一整数进行比较，并产生第一比较信号。 互连被配置为将第一比较信号从第一比较器传送到计数器复位端口。 输出耦合到第一个比较器。 时钟信号具有周期性波形。 和信号表示第一和，它等于计数器复位后由计数器接收的时钟信号的波形数。 在第一实施例中，可以从至少三个连续整数的集合中选择第一整数。 在第二实施例中，时钟信号的频率至少为1.5千兆赫兹。 第三实施例包括第一实施例和第二实施例的特征。

    DOCUMENT HANDLING
    5.
    发明申请
    DOCUMENT HANDLING 有权
    文件处理

    公开(公告)号：US20080062472A1

    公开(公告)日：2008-03-13

    申请号：US11854303

    申请日：2007-09-12

    申请人： Ken Garg ,  Fred Pulzello ,  Mark Chambers ,  Debra Logan-Rabb

    发明人： Ken Garg ,  Fred Pulzello ,  Mark Chambers ,  Debra Logan-Rabb

    IPC分类号： H04N1/00

    CPC分类号： G06K9/00442 ,  G06Q10/06 ,  G06Q10/0633 ,  G06Q10/10

    摘要： Methods of processing incoming documents. The methods may comprise receiving a plurality of documents in electronic form and classifying each of the plurality of documents into at least one of a plurality of document classifications. The methods may also comprise extracting metadata from the plurality of documents. In addition, the methods may comprise executing a first workflow for processing documents classified in a first document classification selected from the plurality of document classifications and executing a second workflow for processing documents classified in a second document classification selected from the plurality of document classifications.

    摘要翻译： 处理传入文件的方法 所述方法可以包括以电子形式接收多个文档，并将多个文档中的每个文档分类成多个文档分类中的至少一个。 该方法还可以包括从多个文档中提取元数据。 此外，所述方法可以包括执行用于处理分类为从所述多个文档分类中选择的第一文档分类中的文档的第一工作流，并执行用于处理分类为从所述多个文档分类中选择的第二文档分类中的文档的第二工作流程。

    Methods and systems to provide a plurality of signals having respective different phases
    7.
    发明申请
    Methods and systems to provide a plurality of signals having respective different phases 失效
    提供具有各自不同相位的多个信号的方法和系统

    公开(公告)号：US20080018406A1

    公开(公告)日：2008-01-24

    申请号：US11902604

    申请日：2007-09-24

    申请人： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

    发明人： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

    IPC分类号： H03L7/00

    CPC分类号： H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

    摘要： A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

    摘要翻译： 一种用于产生具有用于接收参考信号的输入端的多个合成时钟的系统，耦合到所述输入信号端的锁相环电路，其中所述锁相环电路能够产生频率锁定到所述输入信号的多个输出信号 参考信号并且具有多个不同的相位，耦合到锁相环电路的相位旋转器，其中相位旋转器产生更大的多个相位。

    METHODS OF CALCULATING IMPACT TIME FOR STORMS
    8.
    发明申请
    METHODS OF CALCULATING IMPACT TIME FOR STORMS 审中-公开
    计算冲击时间的方法

    公开(公告)号：US20070221743A1

    公开(公告)日：2007-09-27

    申请号：US11690076

    申请日：2007-03-22

    申请人： Robert Weinzapfel ,  Christopher Hebert ,  Mark Chambers

    发明人： Robert Weinzapfel ,  Christopher Hebert ,  Mark Chambers

    IPC分类号： A01G15/00

    CPC分类号： A01G15/00 ,  G01W1/10

    摘要： At least one method for indicating a weather condition includes indexing a storm based on two or more parameters. One of the parameters is a travel speed of the storm and a second parameter is a location of the storm. The method further includes providing a time before the storm impacts a recipient based on the travel speed of the storm and a track distance to the recipient location. The method further includes delivering the time before the storm impacts the location to the recipient.

    摘要翻译： 用于指示天气状况的至少一种方法包括基于两个或多个参数来索引风暴。 其中一个参数是风暴的行驶速度，第二个参数是风暴的位置。 该方法还包括根据风暴的行进速度和到接收位置的轨迹距离，在暴风雨影响接收者之前提供时间。 该方法还包括在风暴影响接收者的位置之前传送时间。

    Voltage controlled oscillator with variable control sensitivity
    9.
    发明申请
    Voltage controlled oscillator with variable control sensitivity 审中-公开
    具有可变控制灵敏度的压控振荡器

    公开(公告)号：US20070152761A1

    公开(公告)日：2007-07-05

    申请号：US11636977

    申请日：2006-12-12

    申请人： Kwang Kim ,  Chun-Ying Chen ,  Mark Chambers

    发明人： Kwang Kim ,  Chun-Ying Chen ,  Mark Chambers

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0995 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/06

    摘要： An embodiment of the invention provides an apparatus and method for varying a voltage controlled oscillator (VCO) sensitivity. A VCO has an oscillator portion coupled to a variable current supply. The variable current supply has one or more enabled variable current cells. The enable variable current cell input provides a control to change the VCO sensitivity. In an example, the oscillator portion has a ring oscillator. In an example, the variable current supply has at least two variable current cells that supply the control current. A binary control signal alters a quantity of variable current cells that supply the control current. Each successive variable current cell has an output current substantially equal to twice that of a prior variable current cell.

    摘要翻译： 本发明的实施例提供了一种用于改变压控振荡器（VCO）灵敏度的装置和方法。 VCO具有耦合到可变电流源的振荡器部分。 可变电流源具有一个或多个使能的可变电流单元。 使能可变电流单元输入提供了改变VCO灵敏度的控制。 在一个示例中，振荡器部分具有环形振荡器。 在一个示例中，可变电流源具有提供控制电流的至少两个可变电流单元。 二进制控制信号改变提供控制电流的可变电流单元的数量。 每个连续的可变电流单元具有基本上等于先前可变电流单元的输出电流的两倍的输出电流。