公开(公告)号：US08289541B2

公开(公告)日：2012-10-16

申请号：US11854303

申请日：2007-09-12

申请人： Ken Garg ,  Fred Pulzello ,  Mark Chambers ,  Debra Logan-Rabb

发明人： Ken Garg ,  Fred Pulzello ,  Mark Chambers ,  Debra Logan-Rabb

IPC分类号： H04N1/00

CPC分类号： G06K9/00442 ,  G06Q10/06 ,  G06Q10/0633 ,  G06Q10/10

摘要： Methods of processing incoming documents. The methods may comprise receiving a plurality of documents in electronic form and classifying each of the plurality of documents into at least one of a plurality of document classifications. The methods may also comprise extracting metadata from the plurality of documents. In addition, the methods may comprise executing a first workflow for processing documents classified in a first document classification selected from the plurality of document classifications and executing a second workflow for processing documents classified in a second document classification selected from the plurality of document classifications.

摘要翻译： 处理传入文件的方法 所述方法可以包括以电子形式接收多个文档，并将多个文档中的每个文档分类成多个文档分类中的至少一个。 该方法还可以包括从多个文档中提取元数据。 此外，所述方法可以包括执行用于处理分类为从所述多个文档分类中选择的第一文档分类中的文档的第一工作流，并执行用于处理分类为从所述多个文档分类中选择的第二文档分类中的文档的第二工作流程。

公开(公告)号：US20110235065A1

公开(公告)日：2011-09-29

申请号：US12729301

申请日：2010-03-23

申请人： Michael S. Wilson ,  Robert Rumford ,  Mark Chambers ,  Thomas Brown

发明人： Michael S. Wilson ,  Robert Rumford ,  Mark Chambers ,  Thomas Brown

IPC分类号： G06T5/00 ,  G06K15/10

CPC分类号： B41J3/28 ,  B41J3/4073 ,  B41J11/0095 ,  B41J25/003

摘要： A printing apparatus for printing within a predefined print zone on a selected surface of a skewed object moving in a given direction of travel includes a bracket, at least two sensors at known positions adjacent to the passing object detecting the leading edge of a given surface, a positioning mechanism mounted on the bracket, a printhead mounted on the positioning mechanism and operable to print on the moving object selected surface, the positioning mechanism operable to position the printhead into a known correct printing position relative to the selected surface, and a controller communicating with the sensors, positioning mechanism, and printhead, and operable to calculate object skew in response to the sensor signals and to operate the positioning mechanism to position the printhead into the known correct printing position and to operate the printhead to print within the predefined print zone on the skewed moving object.

摘要翻译： 用于在给定行进方向上移动的偏斜物体的选定表面上的预定打印区域内打印的打印设备包括托架，在与检测给定表面的前缘的通过对象相邻的已知位置处的至少两个传感器， 安装在所述支架上的定位机构，安装在所述定位机构上并可操作以在所述移动物体选择表面上打印的打印头，所述定位机构可操作以将打印头相对于所选择的表面定位在已知的正确打印位置，以及控制器通信 传感器，定位机构和打印头，并且可操作以响应于传感器信号计算物体歪斜并且操作定位机构以将打印头定位到已知的正确打印位置并且操作打印头以在预定打印区域内打印 在偏斜的移动物体上。

公开(公告)号：US07609095B2

公开(公告)日：2009-10-27

申请号：US11122002

申请日：2005-05-05

申请人： Gerald I. Grand ,  Mark Chambers ,  Baobinh Truong

发明人： Gerald I. Grand ,  Mark Chambers ,  Baobinh Truong

IPC分类号： H03K17/00

CPC分类号： G01R31/31727

摘要： A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

摘要翻译： 用于无缝重新编程时钟频率的系统和方法包括产生CPU和双倍数据速率（DDR）时钟的锁相环（PLL）。 晶体用于产生参考时钟。 CPU时钟和参考时钟是第一多路复用器的输入，DDR时钟和参考时钟是第二个多路复用器的输入。 在正常操作中，多路复用器提供CPU和DDR时钟信号作为输出。 要重新编程时钟频率并复位PLL，（1）参考时钟信号被选择为两个复用器的输出，因此器件在内部参考时钟上运行。 多路复用切换与CPU和DDR时钟信号同步。 （2）PLL重新编程，其内部压控振荡器复位，PLL以新的所需频率重新启动。 （3）当新的PLL频率输出稳定时，多路复用器与参考时钟信号同步切换回PLL生成的CPU和DDR时钟。

公开(公告)号：US07605665B2

公开(公告)日：2009-10-20

申请号：US11802879

申请日：2007-05-25

申请人： Mark Chambers ,  Natarajan Ramachandran ,  Karapet Khanoyan ,  Tong Zhu

发明人： Mark Chambers ,  Natarajan Ramachandran ,  Karapet Khanoyan ,  Tong Zhu

IPC分类号： H03L7/18 ,  H03L7/197

CPC分类号： H03L7/18 ,  H03K23/486 ,  H03L7/081 ,  H03L7/0996 ,  H03L7/1976

摘要： An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal. The fractional frequency divider incrementally selects among all the outputs of the multi-phased VCO according to either a forward phase shifting operation or a backward phase shifting operation to generate a true fractional division factor.

摘要翻译： 公开了一种通过反馈调制来显着降低在分数N锁相环（PLL）中引入的相位噪声的装置和方法。 在PLL的反馈路径中引入了一个分数分频器，以通过有限分数步长产生真正的分数分数因子，以将分辨率提高到等于分数分频器中有限步长的倒数的因子。 提高PLL的分辨率可以降低相位噪声。 分数分频器使用真正的分数分频因子将多相压控振荡器（VCO）的单个输出的频率除以分数除数，以将分频反馈信号的频率与频率参考信号相匹配。 分数分频器根据正向相移操作或反向相移操作在多相VCO的所有输出中递增地选择以产生真正的分数分数因子。

公开(公告)号：US20080290954A1

公开(公告)日：2008-11-27

申请号：US11802879

申请日：2007-05-25

申请人： Mark Chambers ,  Natarajan Ramachandran ,  Karapet Khanoyan ,  Tong Zhu

发明人： Mark Chambers ,  Natarajan Ramachandran ,  Karapet Khanoyan ,  Tong Zhu

IPC分类号： H03L7/08

CPC分类号： H03L7/18 ,  H03K23/486 ,  H03L7/081 ,  H03L7/0996 ,  H03L7/1976

摘要： An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal. The fractional frequency divider incrementally selects among all the outputs of the multi-phased VCO according to either a forward phase shifting operation or a backward phase shifting operation to generate a true fractional division factor.

摘要翻译： 公开了一种通过反馈调制来显着降低在分数N个锁相环（PLL）中引入的相位噪声的装置和方法。 在PLL的反馈路径中引入了一个分数分频器，以通过有限分数步长产生真正的分数分数因子，以将分辨率提高到等于分数分频器中有限步长的倒数的因子。 提高PLL的分辨率可以降低相位噪声。 分数分频器使用真正的分数分频因子将多相压控振荡器（VCO）的单个输出的频率除以分数除数，以将分频反馈信号的频率与频率参考信号相匹配。 分数分频器根据正向相移操作或反向相移操作在多相VCO的所有输出中递增地选择以产生真正的分数分数因子。

公开(公告)号：US20070117847A1

公开(公告)日：2007-05-24

申请号：US11635942

申请日：2006-12-08

申请人： Mark Chambers ,  Philip Jones ,  Helen Szekeres

发明人： Mark Chambers ,  Philip Jones ,  Helen Szekeres

IPC分类号： A61K31/454 ,  C07D409/14

CPC分类号： C07D401/04 ,  A61K31/454 ,  A61K31/497 ,  C07D211/58 ,  C07D401/14 ,  C07D409/14

摘要： The present invention provides a method of treatment of a subject suffering from a disease, such as schizophrenia, for which the administration of an NK-3 antagonist is indicated which comprises administering to that subject a therapeutically effective amount of a compound of formula I: wherein, generally, Q is R1 is benzyl, phenyl, thiophene or imidazolyl optionally substituted with C1-4alkyl or halogen, such as methyl, fluorine or bromine; R2 is hydrogen or C1-4alkyl such as methyl; R3 is phenyl; R4 is hydrogen; R5 is hydrogen or C1-6alkylcarbonyl such as methylcarbonyl; X is —SO2— or —C(O)N(R2)SO2— where R2 is preferably hydrogen; Y is a bond, CH2 or Z1 where Z1 is —N(Rf)— in which Rf is C1-6alkylcarbonyl such as ethylcarbonyl; and R6 is phenyl, pyrazolyl, pyridyl, pyrimidinyl or benzimidazolonyl optionally substituted with one or two groups chosen from C1-6alkyl and benzyl, such as methyl, ethyl and benzyl; or a pharmaceutically acceptable salt thereof.

摘要翻译： 本发明提供治疗患有诸如精神分裂症的受试者的方法，所述疾病包括施用NK-3拮抗剂，其包括向该受试者施用治疗有效量的式I化合物：其中 通常，Q是R 1是苄基，苯基，噻吩或任选被C 1-4烷基或卤素取代的咪唑基，例如甲基，氟或溴; R 2是氢或C 1-4烷基，例如甲基; R 3是苯基; R 4是氢; R 5是氢或C 1-6烷基羰基，例如甲基羰基; X是-SO 2 - 或-C（O）N（R 2）SO 2 - ，其中R 2 O / >优选为氢; Y是键，CH 2或Z 1，其中Z 1是-N（R f）， - 其中R 1是C 1-6烷基羰基，例如乙基羰基; R 6是苯基，吡唑基，吡啶基，嘧啶基或苯并咪唑烷基，任选地被一个或两个选自C 1-6烷基和苄基的基团取代，例如甲基，乙基和 苄基; 或其药学上可接受的盐。

公开(公告)号：US20070098627A1

公开(公告)日：2007-05-03

申请号：US11264126

申请日：2005-11-01

申请人： Terry Marshall ,  Mark Chambers ,  Robert El Wade

发明人： Terry Marshall ,  Mark Chambers ,  Robert El Wade

IPC分类号： C01B3/24

CPC分类号： C01B3/384 ,  C01B2203/0233 ,  C01B2203/0816 ,  C01B2203/0822 ,  C01B2203/0827 ,  C01B2203/0894 ,  F22B13/00 ,  Y02P20/128

摘要： Provided herein is a process for generating steam comprising supplying a first stream to a steam reformer to produce a second stream comprising essentially 100% steam such that the molecular composition of the first stream is identical to the molecular composition of second stream, wherein the steam reformer comprises a reformer inlet in fluid communication with a reformer outlet, and at least one tube arranged between, and in fluid communication with the reformer inlet and the reformer outlet; and wherein the at least one tube is in thermal communication with a furnace of the steam reformer. A steam reformer for producing steam is also disclosed.

摘要翻译： 本文提供了一种产生蒸汽的方法，包括向蒸汽重整器供应第一流以产生包含基本上100％蒸汽的第二料流，使得第一料流的分子组成与第二料流的分子组成相同，其中蒸汽重整器 包括与重整器出口流体连通的重整器入口和布置在重整器入口和重整器出口之间并与重整器入口和重整器出口流体连通的至少一个管; 并且其中所述至少一个管与所述蒸汽重整器的炉子热连通。 还公开了一种用于生产蒸汽的蒸汽重整器。

公开(公告)号：US20050165023A1

公开(公告)日：2005-07-28

申请号：US10512655

申请日：2003-05-01

申请人： Michela Bettati ,  Mark Chambers ,  Simon Goodacre ,  David Hallett ,  Michael Neil ,  Leslie Street

发明人： Michela Bettati ,  Mark Chambers ,  Simon Goodacre ,  David Hallett ,  Michael Neil ,  Leslie Street

IPC分类号： A61K31/53 ,  A61P1/08 ,  A61P1/14 ,  A61P13/10 ,  A61P15/00 ,  A61P21/02 ,  A61P25/00 ,  A61P25/04 ,  A61P25/06 ,  A61P25/08 ,  A61P25/18 ,  A61P25/22 ,  A61P25/24 ,  A61P25/28 ,  A61P25/30 ,  A61P25/32 ,  A61P27/16 ,  C07D487/04

CPC分类号： C07D487/04

摘要： A class of 7-phenylimidazo[1,2-b][1,2,4]triazine derivatives, substituted at the meta position of the phenyl ring by an optionally substituted aryl or heteroaryl group which is directly attached or bridged by an oxygen atom or a —NH— linkage, and substituted on the phenyl ring by one or two further substituents as defined herein, being selective ligands for GABAA receptors, in particular having good affinity for the α2 and/or α3 and/or α5 subunit thereof, are accordingly of benefit in the treatment and/or prevention of adverse conditions of the central nervous system, including anxiety, convulsions and cognitive disorders.

摘要翻译： 一类7-苯基咪唑并[1,2-b] [1,2,4]三嗪衍生物，其在苯环的间位被任选取代的被氧原子连接或桥连的芳基或杂芳基取代 或-NH-键，并且在苯环上被一个或两个如本文所定义的其它取代基取代，是GABA A A受体的选择性配体，特别是对α2和/或α3具有良好的亲和力 和/或其α5亚基因此在治疗和/或预防中枢神经系统的不良状况（包括焦虑，惊厥和认知障碍）方面是有益的。

公开(公告)号：US20050073902A1

公开(公告)日：2005-04-07

申请号：US10832262

申请日：2004-04-27

申请人： Lionel D'Luna ,  Mark Chambers ,  Thomas Hughes ,  Kwang Kim ,  Sathish Radhakrishnan

发明人： Lionel D'Luna ,  Mark Chambers ,  Thomas Hughes ,  Kwang Kim ,  Sathish Radhakrishnan

IPC分类号： G06F13/42 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/00

CPC分类号： G11C7/04 ,  G06F13/4243 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K2005/00052 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/183 ,  H03L7/23

摘要： A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

公开(公告)号：US07515504B2

公开(公告)日：2009-04-07

申请号：US11969404

申请日：2008-01-04

申请人： Lionel J. D'Luna ,  Mark Chambers ,  Thomas Hughes ,  Kwang Y. Kim ,  Sathish K. Radhakrishnan

发明人： Lionel J. D'Luna ,  Mark Chambers ,  Thomas Hughes ,  Kwang Y. Kim ,  Sathish K. Radhakrishnan

IPC分类号： G11C8/00

CPC分类号： G11C7/04 ,  G06F13/4243 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  H03K2005/00052 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/183 ,  H03L7/23

摘要： A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

摘要翻译： 一种系统和方法用于允许电路和外部设备之间的高速通信。 该系统和方法包括配置为被数字控制的多个相控输出的PLL，被配置为将控制器电路的时钟与接口电路对准的偏移校准PLL以及被配置为相移输入信号的相位内插电压控制延迟线。 相位插值的模拟设计技术可精确定位高速接口所需的时钟和选通信号。 高速接口用于从外部设备发送和接收信号，例如DDR DRAM。