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公开(公告)号：US20130313524A1
公开(公告)日：2013-11-28
申请号：US13899666
申请日：2013-05-22
IPC分类号： H01L29/775 , H01L29/66
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/7839 , H01L29/78642 , H01L29/78696
摘要： This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts.
摘要翻译： 本发明描述了一种由具有两个独立栅电极的一个或多个垂直堆叠的栅极全周硅纳米线场效应晶体管（SNWFET）组成的新型电子器件。 作用在晶体管通道的中心部分的两个栅电极之一控制通道的开/关行为。 作用在晶体管的源极和漏极附近的区域上的第二栅极限定了器件的极性，即p或n型。 第二栅极的电场作用于纳米线至源极/漏极区域的接口处或与SiNW体的耗尽区域非常接近的任何位置，调节触点处的肖特基势垒的弯曲，最终筛选一个 电荷载体的类型通过晶体管的沟道。 这是通过调节源极和漏极触点上的肖特基势垒厚度来控制通过晶体管沟道的多数载流子来实现的。
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2.发明授权公开(公告)号：US07995599B2
公开(公告)日：2011-08-09
申请号：US12412742
申请日：2009-03-27
CPC分类号： G06F9/5083 , G06F15/7825
摘要： A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.
摘要翻译： 通过引入复杂的数据包处理机制，为基于片上芯片（NoC）的多核系统提供可靠性，功率管理和负载均衡支持的方法，并通过修改附加到 多核计算系统的核心。 它还提出了利用所提出的硬件扩展的策略。 该目的通过一种用于管理多核系统中的外围元件的负载的方法来实现，该多核系统包括通过NoC访问外围元件的多个处理单元，每个处理单元和连接到网络接口的外围元件，负责格式化和驱动发送到 或从NoC接收，其中，在考虑具有相似功能的至少两个外围元件的同时，专用于第一外围元件的网络接口将输入分组重新路由到专用于第二外围元件的第二网络接口。
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公开(公告)号：US09252252B2
公开(公告)日：2016-02-02
申请号：US13899666
申请日：2013-05-22
IPC分类号： H01L21/00 , H01L21/32 , H01L21/47 , H01L29/775 , H01L29/66 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/786 , B82Y10/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/7839 , H01L29/78642 , H01L29/78696
摘要： This invention describes a novel electronic device consisting of one—or more—vertically stacked gate-all-around silicon nanowire field effect transistor (SNWFET) with two independent gate electrodes. One of the two gate electrodes, acting on the central section of the transistor channel, controls on/off behavior of the channel. The second gate, acting on the regions in proximity to the source and the drain of the transistor, defines the polarity of the devices, i.e. p or n type. The electric field of the second gate acts either at the interface of the nanowire-to-source/drain region or anywhere in close proximity to the depleted region of the SiNW body, modulating the bending of the Schottky barriers at the contacts, eventually screening one type of charge carrier to pass through the channel of the transistor. This is achieved by controlling the majority carriers passing through the transistor channel by regulating the Schottky barrier thicknesses at the source and drain contacts.
摘要翻译： 本发明描述了一种由具有两个独立栅电极的一个或多个垂直堆叠的栅极全周硅纳米线场效应晶体管（SNWFET）组成的新型电子器件。 作用在晶体管通道的中心部分的两个栅电极之一控制通道的开/关行为。 作用在晶体管的源极和漏极附近的区域上的第二栅极限定了器件的极性，即p或n型。 第二栅极的电场作用在纳米线到源极/漏极区的界面处或者靠近SiNW体的耗尽区的任何地方，调节在接触处的肖特基势垒的弯曲，最终筛选一个 电荷载体的类型通过晶体管的沟道。 这是通过调节源极和漏极触点上的肖特基势垒厚度来控制通过晶体管沟道的多数载流子来实现的。
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4.发明申请METHODS FOR HARDWARE REDUCTION AND OVERALL PERFORMANCE IMPROVEMENT IN COMMUNICATION SYSTEM 审中-公开减少硬件的方法和通信系统中的整体性能改进公开(公告)号：US20100002601A1
公开(公告)日：2010-01-07
申请号：US12441008
申请日：2007-09-12
IPC分类号： H04L12/28
CPC分类号： H04L49/101 , G06F17/5045 , H04L49/109
摘要： The aim of the present invention is a method to achieve the customization of the communication network of a multicore communication system. This goal is achieved thanks to a method to design a multicore communication system, said communication system comprising a communication network having a plurality of switches and several elements communicating through the communication network, said method comprising the steps of: a) defining the communication network topology, comprising a number of switches, the architecture of said switches and the interconnection between said switches, b) defining routes to communicate among the elements through the switches according to the application running on the system, c) marking the input-to-output connections used within the switches traversed by these routes, d) removing all or part of the electronic components related to the non-marked connections.
摘要翻译： 本发明的目的是实现多核通信系统的通信网络的定制的方法。 该目的是通过设计多核心通信系统的方法实现的，所述通信系统包括具有多个交换机的通信网络和通过通信网络通信的多个元件，所述方法包括以下步骤：a）定义通信网络拓扑 ，包括多个交换机，所述交换机的架构和所述交换机之间的互连，b）根据在系统上运行的应用来定义通过交换机在元件之间通信的路由; c）标记输入到输出连接 在由这些路线穿过的交换机内使用，d）删除与未标记连接相关的全部或部分电子部件。
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公开(公告)号：US20090313592A1
公开(公告)日：2009-12-17
申请号：US12375525
申请日：2007-10-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08 , H04L49/25
摘要： A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connected switches.
摘要翻译： 一种用于设计用于连接多核系统中的片上组件的基于芯片的基于网络（NoC）的通信系统的方法，所述系统包括通过所述通信系统通信的若干元件，所述通信系统至少包括开关，所述方法包括步骤 对在多核系统上运行的应用进行建模，建立用于连接元件的交换机的数量和配置，为每两对通信元件建立元件和交换机之间的物理连接性：（a）定义通信路径， b）计算由于需要将所述路径变成物理连接性而考虑的度量，考虑到任何先前定义的物理连接性，（c）对多个可能路径迭代步骤a和b，（d）选择具有 最佳度量，以及（e）在交换机之间建立任何丢失的物理连接，使得所选择的最优路径发生 跨物理连接的交换机。
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公开(公告)号：US06467075B1
公开(公告)日：2002-10-15
申请号：US09533808
申请日：2000-03-24
申请人： Koichi Sato , Lcu Semeria , Giovanni De Micheli
发明人： Koichi Sato , Lcu Semeria , Giovanni De Micheli
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemented in hardware or mixed hardware/software systems are making use of complex data structures stored in one or multiple memories. As a result, many of the C/C++ features which were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation/deallocation and pointers used to manage data. This inventors present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. This solution fits current memory management methodologies. It consists of instantiating a hardware allocator tailored to an application and a memory architecture. This work also supports the resolution of pointers without restriction on the data structures. An implementation using the SUIF framework is presented, followed by some case studies such as the realization of a video filter.
摘要翻译： 基于C / C ++的设计方法中最大的挑战之一是有效地将C / C ++模型映射到硬件中。 在硬件或混合硬件/软件系统中实现的许多网络和多媒体应用程序正在利用存储在一个或多个存储器中的复杂数据结构。 因此，最初为软件应用程序设计的许多C / C ++功能现在正在进入硬件。 这些功能包括用于管理数据的动态内存分配/释放和指针。 本发明人提出了一种用于将具有指针和malloc / free的任意C代码有效地映射到硬件的解决方案。 该解决方案适合当前的内存管理方法。 它包括实例化针对应用程序和内存架构量身定制的硬件分配器。 这项工作还支持指针的分辨率，而不受数据结构的限制。 提出了使用SUIF框架的实现方法，其次是一些案例研究，例如实现视频过滤器。
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公开(公告)号：US08042087B2
公开(公告)日：2011-10-18
申请号：US12375525
申请日：2007-10-10
CPC分类号： G06F17/5045 , G06F2217/08 , H04L49/25
摘要： A method to design a Networks on Chips (NoCs)-based communication system for connecting on-chip components in a multicore system, said system comprising several elements communicating through the communication system, said communication system comprising at least switches, said method comprising the steps of modelling the applications running on the multicore system, establishing the number and configuration of switches to connect the elements, establishing physical connectivity between the elements and the switches, for each two pairs of communicating elements: (a) a defining a communication path, (b) calculating metrics as affected by the need to render said path into physical connectivity, taking into account any previously defined physical connectivity, (c) iterating the steps a and b for a plurality of possible paths, (d) choosing the path having the optimal metrics, and (e) establishing any missing physical connectivity between the switches so that the selected optimal path occurs across physically connected switches.
摘要翻译： 一种用于设计用于连接多核系统中的片上组件的基于芯片的基于网络（NoC）的通信系统的方法，所述系统包括通过所述通信系统通信的若干元件，所述通信系统至少包括交换机，所述方法包括步骤 对在多核系统上运行的应用进行建模，建立用于连接元件的交换机的数量和配置，为每两对通信元件建立元件和交换机之间的物理连接性：（a）定义通信路径， b）计算由于需要将所述路径变成物理连接性而考虑的度量，考虑到任何先前定义的物理连接性，（c）对多个可能路径迭代步骤a和b，（d）选择具有 最佳度量，以及（e）在交换机之间建立任何丢失的物理连接，使得所选择的最优路径发生 跨物理连接的交换机。
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8.发明申请公开(公告)号：US20100080124A1
公开(公告)日：2010-04-01
申请号：US12412742
申请日：2009-03-27
IPC分类号： H04L12/56
CPC分类号： G06F9/5083 , G06F15/7825
摘要： A method to provide reliability, power management and load balancing support for multicore systems based on Networks-on-Chip (NoCs) and to efficiently implement architectural support for this method by introducing complex packet handling mechanisms is achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved with a method to manage the load of peripheral elements within a multicore system comprising several processing units accessing peripheral elements through a NoC, each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the NoC, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.
摘要翻译： 通过引入复杂的数据包处理机制，为基于片上芯片（NoC）的多核系统提供可靠性，功率管理和负载均衡支持的方法，并通过修改附加到 多核计算系统的核心。 它还提出了利用所提出的硬件扩展的策略。 该目的通过一种用于管理多核系统中的外围元件的负载的方法来实现，该多核系统包括通过NoC访问外围元件的多个处理单元，每个处理单元和连接到网络接口的外围元件，负责格式化和驱动发送到 或从NoC接收，其中，在考虑具有相似功能的至少两个外围元件的同时，专用于第一外围元件的网络接口将输入分组重新路由到专用于第二外围元件的第二网络接口。
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