公开(公告)号：US08250300B2

公开(公告)日：2012-08-21

申请号：US11415880

申请日：2006-05-01

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： G06F12/00

CPC分类号： G06F12/0895 ,  G06F12/1063 ,  Y02D10/13

摘要： A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.

摘要翻译： 高速缓冲存储器系统包括高速缓冲存储器和高速缓存控制器，其接收第一地址以访问高速缓冲存储器。 高速缓存控制器包括第一地址变换器接收第一地址并将其变换成一个第一高速缓存地址; 第一缓存地址用于访问高速缓冲存储器以检索标签地址部分的第一部分。 高速缓存控制器包括命中检测器，基于检索到的标签地址部分的第一部分与第一地址的第一预定部分的比较建立部分命中条件，第二地址变换器接收第一地址并将其转换 进入一秒缓存地址。 高速缓存控制器使用一秒高速缓存地址来访问高速缓冲存储器以在建立部分命中条件的情况下检索数据字。

公开(公告)号：US20100135435A1

公开(公告)日：2010-06-03

申请号：US12622054

申请日：2009-11-19

申请人： Giuseppe Visalli ,  Giuseppe Avellone

发明人： Giuseppe Visalli ,  Giuseppe Avellone

IPC分类号： H04L27/38

CPC分类号： H04L25/0224 ,  H04L25/061 ,  H04L27/32 ,  H04L27/3818

摘要： The method is for estimating the fading coefficients of a plurality of transmission channels on which signals to be sent, generated as a function of a sequence of symbols, are transmitted according to a particular modulation, e.g. AM-PSK modulation. The fading coefficients are estimated by using estimations of the transmitted symbols obtained in advance, thus obtaining DC components of the received signal by coherent demodulation locked to the phases of the transmitted AM-PSK signals, and processing these DC components. The method may not require the choice of a stochastic distribution model of the channel fading, thus it remains efficient even when the channel characteristics vary significantly. Moreover, the method works correctly even if the received stream is disturbed by inter-symbolic interference (ISI) and/or by multi-path fading.

摘要翻译： 该方法是用于估计多个传输信道的衰落系数，其上根据特定调制发送作为符号序列生成的要发送的信号，例如， AM-PSK调制。 通过使用预先获得的发送符号的估计来估计衰落系数，从而通过锁定到发送的AM-PSK信号的相位的相干解调获得接收信号的DC分量，并处理这些DC分量。 该方法可能不需要选择信道衰落的随机分布模型，因此即使当信道特性显着变化时，仍然保持有效。 此外，即使接收的流被符号间干扰（ISI）和/或多路径衰落干扰，该方法也能正常工作。

公开(公告)号：US07424068B2

公开(公告)日：2008-09-09

申请号：US10930715

申请日：2004-08-30

申请人： Giuseppe Visalli ,  Francesco Pappalardo ,  Giuseppe Avellone ,  Francesco Rimi ,  Agostino Galluzzo

发明人： Giuseppe Visalli ,  Francesco Pappalardo ,  Giuseppe Avellone ,  Francesco Rimi ,  Agostino Galluzzo

IPC分类号： H03D3/18

CPC分类号： H04L1/0059 ,  H03M13/256 ,  H04L1/0054 ,  H04L1/0068 ,  H04L25/067 ,  H04L27/2272 ,  H04L2027/0055 ,  H04L2027/0067

摘要： A method for decoding signals with encoded symbols over a symbol interval that modulate a carrier. The method includes phase locking the signal to be decoded to obtain a phase-locked signal. The value assumed by the phase-locked signal on at least one subinterval in each symbol interval is detected. The method continues with attributing to the decoded symbol corresponding to each symbol interval a value that is a function of the value detected the subinterval. The subinterval in question can be a single subinterval located at the end of the symbol interval. Alternatively, the value assumed by the phase-locked signal on a plurality of subintervals in each symbol interval is detected, and a respective majority value of said phase-locked signal within said plurality of subintervals is identified. A value determined on the basis of the majority value is attributed to the decoded symbol corresponding to each symbol interval.

摘要翻译： 一种用于在调制载体的符号间隔上对具有编码符号的信号进行解码的方法。 该方法包括对要解码的信号进行锁相以获得锁相信号。 检测每个符号间隔中的至少一个子间隔上的锁相信号所假设的值。 该方法继续归因于对应于每个符号间隔的解码符号，该值是检测到子间隔的值的函数。 所涉及的子间隔可以是位于符号间隔结束处的单个子间隔。 或者，检测每个符号间隔中的多个子间隔上的锁相信号所假设的值，并且识别所述多​​个子区间内的所述锁相信号的相应多数值。 基于多数值确定的值归因于对应于每个符号间隔的解码符号。

公开(公告)号：US07313332B2

公开(公告)日：2007-12-25

申请号：US10830490

申请日：2004-04-21

申请人： Francesco Pappalardo ,  Giuseppe Visalli

发明人： Francesco Pappalardo ,  Giuseppe Visalli

IPC分类号： H04B10/04

CPC分类号： H04L25/4908 ,  H04B10/524

摘要： A data stream (b(t)) including high (“1”) and low (“0”) logical states is transmitted over an optical link by means of an optical source adapted to be driven via the data strema, to generate an optical signal for transmission over the optical link. The optical signal includes optical pulses generated at the occurrence of high logical states in the data stream b(t). The input data stream b(t) is coded into a coded data stream B(t) prior to the transmission over the optical link. The coding step minimizes the logical high states in the coded data stream, and the optical source is driven by means of the coded data stream wherein the number of logical high states has been minimized.

摘要翻译： 包括高（“1”）和低（“0”）逻辑状态的数据流（b（t））通过适于经由数据串的驱动的光源在光链路上传输，以产生光 用于在光链路上传输的信号。 光信号包括在数据流b（t）中出现高逻辑状态时产生的光脉冲。 输入数据流b（t）在通过光链路的传输之前被编码为编码数据流B（t）。 编码步骤使编码数据流中的逻辑高状态最小化，并且通过其中逻辑高状态数已被最小化的编码数据流来驱动光源。

公开(公告)号：US07283460B1

公开(公告)日：2007-10-16

申请号：US11397924

申请日：2006-04-03

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： H04J1/12 ,  H03H7/30

CPC分类号： H04B3/32

摘要： Data are transmitted over a bus including a plurality of lines, wherein energy is dissipated as a result of data transmission. Preferably, the data to be transmitted in parallel are partitioned in a plurality of clusters of data bits. Each cluster is subject to re-ordering according to a set of reordering patterns to produce a corresponding set of respective candidate clusters of data bits. Crosstalk activity values related to transmitting the various candidate clusters are calculated and compared to identify an optimum cluster of data bits that minimizes the energy dissipated as a result of transmission by jointly minimizing the switching activity and the crosstalk activity. The optimum cluster of data bits so identified is then used for transmission over the bus. The optimum cluster of data bits thus causes those bits that give rise to high crosstalk activity to be allotted to bus lines having lower crosstalk capacitance values.

摘要翻译： 数据通过包括多条线路的总线传输，其中能量作为数据传输的结果消散。 优选地，要并行发送的数据被分割成多个数据比特簇。 每个簇根据一组重排序模式进行重新排序，以产生相应的一组相应候选的数据比特簇。 与传输各种候选聚类相关的串扰活动值被计算并进行比较以识别通过共同最小化切换活动和串扰活动而最小化作为传输结果消耗的能量的最佳数据比特簇。 然后将如此识别的最佳数据比特簇用于通过总线传输。 因此，数据位的最佳簇因此将引起高串扰活动的那些位分配给具有较低串扰电容值的总线。

公开(公告)号：US08126084B2

公开(公告)日：2012-02-28

申请号：US12844451

申请日：2010-07-27

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： H04L27/00 ,  H03K9/00

CPC分类号： H04L12/2856

摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

摘要翻译： 用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。 处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的， 根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。

公开(公告)号：US07398289B2

公开(公告)日：2008-07-08

申请号：US10887225

申请日：2004-07-08

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： G06F7/487

CPC分类号： G06F7/4876 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49947

摘要： In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

摘要翻译： 在用于以符号，指数和尾数二进制方式编码的浮点实数的乘法的方法中，尾数的乘法设想了部分乘积的计算步骤，该部分乘积由对应于尾数的一组附加物构成 。 为了减小设计用于计算的电路的尺寸和功率消耗，采用二进制编码方法，其设想将尾数的第一位设置为值1，以便获得包含在0.5之间的值的尾数 还提出了用于实现乘法的产品和电路的舍入的方法。 还示出了根据IEEE754标准从浮点实数转换和编码的电路。 优先应用于便携式和/或无线电子设备，例如移动电话和PDA，具有低功耗要求。

公开(公告)号：US07330867B2

公开(公告)日：2008-02-12

申请号：US10737697

申请日：2003-12-15

申请人： Francesco Pappalardo ,  Giuseppe Visalli

发明人： Francesco Pappalardo ,  Giuseppe Visalli

IPC分类号： G06F7/485

CPC分类号： G06F7/4876 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49947

摘要： In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

公开(公告)号：US20070229324A1

公开(公告)日：2007-10-04

申请号：US11397924

申请日：2006-04-03

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： H03M7/38

CPC分类号： H04B3/32

摘要： Data are transmitted over a bus including a plurality of lines, wherein energy is dissipated as a result of data transmission. Preferably, the data to be transmitted in parallel are partitioned in a plurality of clusters of data bits. Each cluster is subject to re-ordering according to a set of reordering patterns to produce a corresponding set of respective candidate clusters of data bits. Crosstalk activity values related to transmitting the various candidate clusters are calculated and compared to identify an optimum cluster of data bits that minimizes the energy dissipated as a result of transmission by jointly minimizing the switching activity and the crosstalk activity. The optimum cluster of data bits so identified is then used for transmission over the bus. The optimum cluster of data bits thus causes those bits that give rise to high crosstalk activity to be allotted to bus lines having lower crosstalk capacitance values.

摘要翻译： 数据通过包括多条线路的总线传输，其中能量作为数据传输的结果消散。 优选地，要并行发送的数据被分割成多个数据比特簇。 每个簇根据一组重排序模式进行重新排序，以产生相应的一组相应候选的数据比特簇。 与传输各种候选聚类相关的串扰活动值被计算并进行比较以识别通过共同最小化切换活动和串扰活动而最小化作为传输结果消耗的能量的最佳数据比特簇。 然后将如此识别的最佳数据比特簇用于通过总线传输。 因此，数据位的最佳簇因此将引起高串扰活动的那些位分配给具有较低串扰电容值的总线。

公开(公告)号：US20060271723A1

公开(公告)日：2006-11-30

申请号：US11415880

申请日：2006-05-01

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： G06F12/08

CPC分类号： G06F12/0895 ,  G06F12/1063 ,  Y02D10/13

摘要： A cache memory system, comprising at least one cache memory and a cache memory controller. The at least one cache memory includes a plurality of storage locations, each one identified by a corresponding cache address and being adapted to store tag address portions and data words, each data word corresponding to a respective tag address portion. The cache memory controller is adapted to receive a first address and to access the at least one cache memory based on the received first address. The cache memory controller includes a first address transformer adapted to receive the first address and to transform it into at least one first cache address corresponding thereto by applying a first transform function; the at least one first cache address is used by the cache memory controller for accessing the at least one cache memory to retrieve at least a first part of a tag address portion stored in at least one of the storage locations. The cache memory controller includes a hit detector adapted to establish an at least partial hit condition based on a comparison of the retrieved at least a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer adapted to receive the first address and to transform it into at least one second cache address corresponding thereto by applying a second transform function. The cache memory controller is further adapted to use the at least one second cache address for accessing the at least one cache memory to retrieve a data word corresponding to the retrieved tag address portion in case said at least partial hit condition is established.

摘要翻译： 一种高速缓冲存储器系统，包括至少一个高速缓冲存储器和高速缓冲存储器控制器。 所述至少一个高速缓存存储器包括多个存储位置，每个存储位置由相应的高速缓存地址标识，并且适于存储标签地址部分和数据字，每个数据字对应于相应的标签地址部分。 高速缓冲存储器控制器适于接收第一地址并且基于接收的第一地址来访问至少一个高速缓冲存储器。 高速缓存存储器控制器包括：第一地址变换器，适于接收第一地址，并通过应用第一变换函数将其变换成与之对应的至少一个第一高速缓存地址; 所述至少一个第一高速缓存地址被所述高速缓冲存储器控制器用于访问所述至少一个高速缓冲存储器以检索存储在所述存储位置中的至少一个中的标签地址部分的至少第一部分。 高速缓冲存储器控制器包括命中检测器，其适于基于检索到的标签地址部分的至少第一部分和第一地址的第一预定部分的比较来建立至少部分命中条件，以及适配的第二地址变换器 以通过应用第二变换函数来接收第一地址并将其变换成与之对应的至少一个第二高速缓存地址。 高速缓冲存储器控制器还适于在建立所述至少部分命中条件的情况下，使用所述至少一个第二高速缓存地址来访问所述至少一个高速缓冲存储器以检索对应于所检索的标签地址部分的数据字。