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公开(公告)号：US20100312970A1
公开(公告)日：2010-12-09
申请号：US12478555
申请日：2009-06-04
申请人： Gordon B. Bell , Anil Krishna , Brian M. Rogers , Ken V. Vu
发明人： Gordon B. Bell , Anil Krishna , Brian M. Rogers , Ken V. Vu
CPC分类号： G06F12/121
摘要： The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold activity level. A least important cache line is located in the cache responsive to a determination that the threshold activity level is exceeded, wherein the least important cache line is located using a cache replacement scheme. It is determined whether the least important cache line is clean responsive to the determination that the threshold activity level is exceeded. The least important cache line is selected for replacement in the cache responsive to a determination that the least important cache line is clean. A clean cache line is located within a subset of the number of cache lines and selecting the clean cache line for replacement responsive to an absence of a determination that the least important cache line is not clean, wherein the each cache line in the subset is examined in ascending order of importance according to the cache replacement scheme.
摘要翻译： 说明性实施例提供了用于管理高速缓存中的多条高速缓存行的方法，装置和计算机程序产品。 在一个说明性实施例中，确定与高速缓存通信的存储器总线上的活动是否超过阈值活动级别。 响应于确定超出了阈值活动级别，至少重要的高速缓存行位于缓存中，其中使用高速缓存替换方案来定位最不重要的高速缓存行。 响应于超过阈值活动水平的确定，确定最不重要的高速缓存行是否是干净的。 响应于确定最不重要的高速缓存行是干净的，在缓存中选择最不重要的高速缓存行用于替换。 干净的高速缓存行位于高速缓存行数的一个子集内，并且响应于不存在最不重要的高速缓存行不干净的确定，选择干净的高速缓存行进行替换，其中检查子集中的每个高速缓存行 按照缓存替换方案的重要性升序排列。
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公开(公告)号：US20090157968A1
公开(公告)日：2009-06-18
申请号：US11954936
申请日：2007-12-12
申请人： Gordon B. Bell , Anil Krishna , Nicholas D. Lindbert , Ken V. Vu
发明人： Gordon B. Bell , Anil Krishna , Nicholas D. Lindbert , Ken V. Vu
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A cache memory including a plurality of sets of cache lines, and providing an implementation for increasing the associativity of selected sets of cache lines including the combination of providing a group of parameters for determining the worthiness of a cache line stored in a basic set of cache lines, providing a partner set of cache lines, in the cache memory, associated with the basic set, applying the group of parameters to determine the worthiness level of a cache line in the basic set and responsive to a determination of a worthiness in excess of a predetermined level, for a cache line, storing said worthiness level cache line in said partner set.
摘要翻译： 一种高速缓冲存储器，包括多组高速缓存行，并且提供用于增加所选择的高速缓存行集合的关联性的实现，包括提供用于确定存储在基本高速缓存中的高速缓存行的价值的一组参数的组合 在高速缓冲存储器中提供与基本集合相关联的一组高速缓存行，应用该组参数以确定基本集合中的高速缓存行的有效性水平，并且响应于超过 用于高速缓存行的预定级别，将所述有价值级别的高速缓存行存储在所述伙伴集合中。
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3.发明授权Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitecture 有权检查点处理和恢复核心微架构中的无序检查点回收公开(公告)号：US09262170B2
公开(公告)日：2016-02-16
申请号：US13558750
申请日：2012-07-26
CPC分类号： G06F9/3836 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
摘要翻译： 以不同于创建检查点的顺序的顺序回收系统中的检查点。 回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。 当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。
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4.发明申请Out-of-Order Checkpoint Reclamation in a Checkpoint Processing and Recovery Core Microarchitecture 有权检查点处理和恢复核心微体系结构中的无序检查点回收公开(公告)号：US20140032884A1
公开(公告)日：2014-01-30
申请号：US13558750
申请日：2012-07-26
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
摘要翻译： 以不同于创建检查点的顺序的顺序回收系统中的检查点。 回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。 当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。
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公开(公告)号：US08572325B2
公开(公告)日：2013-10-29
申请号：US12961798
申请日：2010-12-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F2212/282
摘要： Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.
摘要翻译： 本发明的实施例旨在优化分割盘高速缓存的性能。 在一个实施例中，磁盘高速缓存包括具有读取部分和写入部分的主区域以及还包括读取部分和写入部分的一个或多个更小的采样区域。 主区域和一个或多个采样区域各自具有读取部分与写入部分的独立可调比率。 高速缓存的读取分布在主要和采样区域的读取部分之间，而高速缓存的写入分布在主要和样本区域的写入部分之间。 跟踪主区域的性能和样本区域的性能，例如通过在预定义的间隔期间获得每个区域的命中率。 然后根据一个或多个样品区域的性能选择性地调节主区域的读/写比。
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公开(公告)号：US20100274973A1
公开(公告)日：2010-10-28
申请号：US12429754
申请日：2009-04-24
CPC分类号： G06F12/0846 , G06F12/0811
摘要： Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions.
摘要翻译： 预期在非均匀缓存访问（NUCA）高速缓存中动态地重组高速缓存线的数据的实施例。 各种实施例包括具有与一个或多个NUCA高速缓存元件耦合的一个或多个处理器的计算设备。 NUCA高速缓存元件可以包括一个或多个高速缓冲存储器组，其中高速缓存的方式在多个存储体之间水平分布。 为了改善处理器对数据的访问等待时间，计算设备可以使用高速缓存行来将缓存线路动态地传播到更靠近处理器的存储体中。 为了实现这种动态重组，实施例可以保持高速缓存行的“方向”位。 方向位可以指示哪个处理器应该移动数据。 此外，实施例可以使用方向位来进行高速缓存行移动决定。
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公开(公告)号：US20120144109A1
公开(公告)日：2012-06-07
申请号：US12961798
申请日：2010-12-07
CPC分类号： G06F12/0871 , G06F2212/282
摘要： Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.
摘要翻译： 本发明的实施例涉及优化分割盘高速缓存的性能。 在一个实施例中，磁盘高速缓存包括具有读取部分和写入部分的主区域以及还包括读取部分和写入部分的一个或多个更小的采样区域。 主区域和一个或多个采样区域各自具有读取部分与写入部分的独立可调比率。 高速缓存的读取分布在主要和采样区域的读取部分之间，而高速缓存的写入分布在主要和样本区域的写入部分之间。 跟踪主区域的性能和样本区域的性能，例如通过在预定义的间隔期间获得每个区域的命中率。 然后根据一个或多个样品区域的性能选择性地调节主区域的读/写比。
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公开(公告)号：US08140758B2
公开(公告)日：2012-03-20
申请号：US12429754
申请日：2009-04-24
IPC分类号： G06F15/163
CPC分类号： G06F12/0846 , G06F12/0811
摘要： Embodiments that dynamically reorganize data of cache lines in non-uniform cache access (NUCA) caches are contemplated. Various embodiments comprise a computing device, having one or more processors coupled with one or more NUCA cache elements. The NUCA cache elements may comprise one or more banks of cache memory, wherein ways of the cache are horizontally distributed across multiple banks. To improve access latency of the data by the processors, the computing devices may dynamically propagate cache lines into banks closer to the processors using the cache lines. To accomplish such dynamic reorganization, embodiments may maintain “direction” bits for cache lines. The direction bits may indicate to which processor the data should be moved. Further, embodiments may use the direction bits to make cache line movement decisions.
摘要翻译： 预期在非均匀缓存访问（NUCA）高速缓存中动态地重组高速缓存线的数据的实施例。 各种实施例包括具有与一个或多个NUCA高速缓存元件耦合的一个或多个处理器的计算设备。 NUCA高速缓存元件可以包括一个或多个高速缓冲存储器组，其中高速缓存的方式在多个存储体之间水平分布。 为了改善处理器对数据的访问等待时间，计算设备可以使用高速缓存行来将缓存线路动态地传播到更靠近处理器的存储体中。 为了实现这种动态重组，实施例可以保持高速缓存行的“方向”位。 方向位可以指示哪个处理器应该移动数据。 此外，实施例可以使用方向位来进行高速缓存行移动决定。
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公开(公告)号：US08543767B2
公开(公告)日：2013-09-24
申请号：US13488215
申请日：2012-06-04
申请人： Gordon B. Bell , Gordon T. Davis , Jeffrey H. Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
发明人： Gordon B. Bell , Gordon T. Davis , Jeffrey H. Derby , Anil Krishna , Srinivasan Ramani , Ken Vu , Steve Woolet
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/6026
摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.
摘要翻译： 处理系统包括被配置为处理应用的存储器和第一核心。 第一个核心包括第一个缓存。 处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。 所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。 第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。
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