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公开(公告)号：US08176281B2
公开(公告)日：2012-05-08
申请号：US12064381
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC: G06F12/00
CPC classification number: G01R31/31719 , G01R31/318533 , G06F21/74 , G11C29/48 , G11C2029/0401 , G11C2029/5602
Abstract: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.
Abstract translation: 微控制器（30）包括处理器（32），可操作地耦合到处理器（32）的嵌入式存储器（46）和可操作地连接到处理器（32）和存储器（36）的微控制器测试接口（34）。 微控制器（30）响应复位信号以执行复位启动，其使得测试接口（34）的初始禁用状态被设置并且与处理器（32）一起执行启动代码。 该代码执行可选地建立进一步的禁用状态。 微控制器（30）在复位开始之后的微控制器（30）操作期间提供用于存储器（46）访问测试交错（34）的测试接口的使能状态，除非进一步禁用的存储器（46）访问状态由 启动代码的执行。
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Patent Agency Ranking
公开(公告)号：US20090254691A1
公开(公告)日：2009-10-08
申请号：US12064375
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava
CPC classification number: G06F1/0321 , G06F15/7842
Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
Abstract translation: 本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。 处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。 波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列 的指令来执行不同的过程。
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公开(公告)号：US20090222652A1
公开(公告)日：2009-09-03
申请号：US12064377
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
CPC classification number: G06F12/1433
Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
Abstract translation: 本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。 存储器（46）可通过测试接口（34）访问。 响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。 测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码 以在随后的微控制器（30）操作期间提供禁用状态。
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公开(公告)号：US08065512B2
公开(公告)日：2011-11-22
申请号：US12064377
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
CPC classification number: G06F12/1433
Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
Abstract translation: 本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。 存储器（46）可通过测试接口（34）访问。 响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。 测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码 以在随后的微控制器（30）操作期间提供禁用状态。
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公开(公告)号：US20090204779A1
公开(公告)日：2009-08-13
申请号：US12064381
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava
CPC classification number: G01R31/31719 , G01R31/318533 , G06F21/74 , G11C29/48 , G11C2029/0401 , G11C2029/5602
Abstract: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.
Abstract translation: 微控制器（30）包括处理器（32），可操作地耦合到处理器（32）的嵌入式存储器（46）和可操作地连接到处理器（32）和存储器（36）的微控制器测试接口（34）。 微控制器（30）响应复位信号以执行复位启动，其使得测试接口（34）的初始禁用状态被设置并且与处理器（32）一起执行启动代码。 该代码执行可选地建立进一步的禁用状态。 微控制器（30）在复位开始之后的微控制器（30）操作期间提供用于存储器（46）访问测试交错（34）的测试接口的使能状态，除非进一步禁用的存储器（46）访问状态由 启动代码的执行。
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公开(公告)号：US07945718B2
公开(公告)日：2011-05-17
申请号：US12064375
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava
CPC classification number: G06F1/0321 , G06F15/7842
Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
Abstract translation: 本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。 处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。 波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列 的指令来执行不同的过程。
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