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公开(公告)号：US07945718B2
公开(公告)日：2011-05-17
申请号：US12064375
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava
CPC classification number: G06F1/0321 , G06F15/7842
Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
Abstract translation: 本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。 处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。 波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列 的指令来执行不同的过程。
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2.发明申请Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set 审中-公开具有具有可编程优先级的中断结构的微控制器，每个优先级与不同的寄存器组相关联公开(公告)号：US20060206646A1
公开(公告)日：2006-09-14
申请号：US10566515
申请日：2004-07-29
Applicant: Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig Mackenna
Inventor： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig Mackenna
CPC classification number: G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
Abstract: Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.
Abstract translation: 通常，对于处理系统，必须保证在第一个程序流的执行恢复之前所有中断的程序流参数都被恢复。 如果在此传输期间发生中断，则所有数据可能不被存储或恢复。 如果不发生程序寄存器内容和其他关键的第一程序流数据的无错误存储，则处理器（180）无法知道还原到寄存器的第一程序流数据是否已经被破坏。 因此，提供了一种新颖的寄存器架构（120,121,122,123,124,125），其便于中断程序流的处理，而不存储和恢复中断的程序流关键数据。
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公开(公告)号：US20120053983A1
公开(公告)日：2012-03-01
申请号：US13196999
申请日：2011-08-03
Applicant: Sameer Vittal , Gerald A. Curtin , Kamal Mannar , Pankaj Shrivastava
Inventor： Sameer Vittal , Gerald A. Curtin , Kamal Mannar , Pankaj Shrivastava
IPC: G06Q10/00
CPC classification number: G06Q10/0635 , F03D17/00 , F03D80/50 , F05B2260/84 , G06Q10/06 , G06Q50/06 , Y02E10/72
Abstract: A system for managing risk associated with a full-service agreement (FSA) for at least one wind turbine is provided. The system includes a memory device configured to store data including at least a plurality of service reports regarding the at least one wind turbine and a processor unit coupled to the memory device. The processor unit includes a programmable hardware component that is programmed. The processor unit is configured to analyze, by a text-mining system, text in the plurality of service reports to output failure information regarding the at least one wind turbine, receive, by a top-down simulator, the failure information from the text-mining system to perform a simulation that generates a distribution model, and receive, by a bottom-up simulator, the failure information from the text-mining system to perform a simulation that generates an extrapolation model.
Abstract translation: 提供了一种用于管理与至少一个风力涡轮机的全业务协议（FSA）相关联的风险的系统。 该系统包括被配置为存储包括关于至少一个风力涡轮机的至少多个服务报告和耦合到该存储器设备的处理器单元的数据的存储器设备。 处理器单元包括被编程的可编程硬件组件。 处理器单元被配置为通过文本挖掘系统分析多个服务报告中的文本以输出关于至少一个风力涡轮机的故障信息，由自顶向下的模拟器接收来自文本 - 采矿系统执行生成分布模型的模拟，并且由自下而上的模拟器接收来自文本挖掘系统的故障信息以执行产生外推模型的模拟。
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公开(公告)号：US20090254691A1
公开(公告)日：2009-10-08
申请号：US12064375
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava
CPC classification number: G06F1/0321 , G06F15/7842
Abstract: One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
Abstract translation: 本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。 处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。 波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列 的指令来执行不同的过程。
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公开(公告)号：US20090222652A1
公开(公告)日：2009-09-03
申请号：US12064377
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
CPC classification number: G06F12/1433
Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
Abstract translation: 本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。 存储器（46）可通过测试接口（34）访问。 响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。 测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码 以在随后的微控制器（30）操作期间提供禁用状态。
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Patent Agency Ranking
公开(公告)号：US07405369B2
公开(公告)日：2008-07-29
申请号：US11161569
申请日：2005-08-08
Applicant: Pothakamuri Mukharzi , Pankaj Shrivastava , Sundaresh Holla
Inventor： Pothakamuri Mukharzi , Pankaj Shrivastava , Sundaresh Holla
CPC classification number: H01H9/223
Abstract: Switch apparatus is disclosed. The switch apparatus has an enclosure, having a openable cover, a switch disposed within the enclosure, a handle in operative communication with the switch, a spring in biasing communication with the handle, and interlocking members. The interlocking members, the handle, the biasing spring and the switch having positions relative to each other such that the interlocking members lock the cover in a closed position in response to the handle being biased toward an OFF position, and the switch contacts being closed. Further disclosed is a method for unlocking a closed cover of a switch apparatus. A spring biased handle is changed to an OFF biased position from an ON biased position passing through a non-biased position. Subsequent thereto, a switch being changed from a closed circuit to an open circuit position. Subsequent thereto, interlocking members are changed from an interlocked to a non-interlocked position.
Abstract translation: 公开了开关装置。 开关装置具有外壳，具有可打开的盖，设置在外壳内的开关，与开关可操作地连通的手柄，与手柄偏置连接的弹簧和互锁构件。 互锁构件，手柄，偏置弹簧和开关具有相对于彼此的位置，使得互锁构件响应于手柄被偏压到关闭位置而将盖锁定在关闭位置，并且开关触点被关闭。 还公开了一种用于解锁开关装置的封闭盖的方法。 弹簧偏置把手从通过非偏置位置的ON偏置位置改变到OFF偏置位置。 随后，开关从闭合电路改变到开路位置。 随后，互锁构件从互锁状态变为非互锁位置。
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7.发明授权Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set 有权具有具有可编程优先级的中断结构的微控制器，每个优先级与不同的寄存器组相关联公开(公告)号：US08392641B2
公开(公告)日：2013-03-05
申请号：US12785943
申请日：2010-05-24
Applicant: Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig MacKenna
Inventor： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig MacKenna
IPC: G06F13/24
CPC classification number: G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
Abstract translation: 本公开的方面涉及具有特别配置的微控制器的系统。 在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。
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公开(公告)号：US08065512B2
公开(公告)日：2011-11-22
申请号：US12064377
申请日：2006-08-22
Applicant: Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
Inventor： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
CPC classification number: G06F12/1433
Abstract: One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
Abstract translation: 本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。 存储器（46）可通过测试接口（34）访问。 响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。 测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码 以在随后的微控制器（30）操作期间提供禁用状态。
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9.发明申请Microcontroller with an Interrupt Structure Having Programmable Priority Levels with each Priority Level Associated with a Different Register Set 有权具有中断结构的微控制器，具有与不同寄存器集相关联的每个优先级的可编程优先级公开(公告)号：US20100299471A1
公开(公告)日：2010-11-25
申请号：US12785943
申请日：2010-05-24
Applicant: Pankaj Shrivastava , Gregory Goodhue , Ata khan , Zhimin Ding , Craig Mackenna
Inventor： Pankaj Shrivastava , Gregory Goodhue , Ata khan , Zhimin Ding , Craig Mackenna
IPC: G06F13/24
CPC classification number: G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
Abstract: Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
Abstract translation: 本公开的方面涉及具有特别配置的微控制器的系统。 在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。
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公开(公告)号：US06464102B1
公开(公告)日：2002-10-15
申请号：US09669537
申请日：2000-09-26
Applicant: Jason Harmon , Ranganadha Kumar Erra , Pankaj Shrivastava , Prakash Viswanathan
Inventor： Jason Harmon , Ranganadha Kumar Erra , Pankaj Shrivastava , Prakash Viswanathan
IPC: B65D4316
CPC classification number: H05K5/0221 , Y10T292/0901 , Y10T292/0902
Abstract: A housing for a circuit breaker motor operating mechanism is disclosed. The housing comprises a base having a plurality of walls connected to a floor thereby defining an interior volume; a cover hingedly attached to one wall of the plurality of walls; and a locking device including a first member connected to the base and a second member connected to the cover and engaged to the first member, the locking device positively securing the cover to the base thereby enclosing the interior volume.
Abstract translation: 公开了一种用于断路器电动机操作机构的壳体。 壳体包括具有连接到地板的多个壁的底座，从而限定内部空间; 盖子铰接地附接到所述多个壁的一个壁; 以及锁定装置，其包括连接到所述基座的第一构件和连接到所述盖并与所述第一构件接合的第二构件，所述锁定装置将所述盖正确地固定到所述底座，从而封闭所述内部容积。
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