公开(公告)号：US06251764B1

公开(公告)日：2001-06-26

申请号：US09439368

申请日：1999-11-15

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Guan Ping Wu

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Guan Ping Wu

IPC分类号： H01L213205

CPC分类号： H01L21/31116 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/6659

摘要： A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces. This etching through results in a tapered, L-shaped sidewall profile, and the integrated circuit device is completed.

摘要翻译： 已经实现了形成氮化硅侧壁间隔物的新方法。 该方法用于使用可以在本发明中进行的两步蚀刻工艺来制造锥形的L形间隔件型材。 根据本发明的目的，已经实现了形成氮化硅侧壁间隔物的新方法。 设置在半导体衬底上的隔离区域。 导电迹线被覆盖在绝缘体层上。 衬底氧化层沉积在导电迹线和绝缘体层上。 沉积覆盖衬垫氧化物层的氮化硅层。 氮化硅层被各向异性地向下蚀刻以减小氮化硅层的垂直厚度，同时不暴露下面的衬里氧化物层。 蚀刻氮化硅层以形成邻近导电迹线的氮化硅侧壁间隔物。 该蚀刻导致锥形的L形侧壁轮廓，并且集成电路器件完成。

公开(公告)号：US06277700B1

公开(公告)日：2001-08-21

申请号：US09480272

申请日：2000-01-11

申请人： Jie Yu ,  Guan Ping Wu ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jie Yu ,  Guan Ping Wu ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L21/31116

摘要： A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.

摘要翻译： 一种在栅极结构旁边蚀刻氮化硅间隔物的方法，包括：在衬底上的栅氧化层上提供栅电极。 衬底氧化物层设置在衬底和栅电极之上。 在衬垫氧化物层上提供氮化硅层。 本发明的氮化物蚀刻配方在等离子体蚀刻器中进行，以各向异性地蚀刻氮化硅层以产生间隔物。 氮化物蚀刻配方包括主蚀刻步骤和过蚀刻步骤。 主蚀刻步骤包括以下条件：在35和55摩尔％之间的Cl 2流动，He流动在35和55摩尔％之间，背面He压力在4和10托之间; 7.5至12.5摩尔％的HBr流量; 压力在400至900 mTorr之间; 功率在300至600瓦之间。 蚀刻配方提供了约1：1的间隔物宽度与氮化物层厚度比，并且不会沉积Si衬底表面。