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公开(公告)号：US06251764B1
公开(公告)日：2001-06-26
申请号：US09439368
申请日：1999-11-15
IPC分类号： H01L213205
CPC分类号： H01L21/31116 , H01L21/3185 , H01L21/76832 , H01L21/76834 , H01L29/6659
摘要： A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces. This etching through results in a tapered, L-shaped sidewall profile, and the integrated circuit device is completed.
摘要翻译： 已经实现了形成氮化硅侧壁间隔物的新方法。 该方法用于使用可以在本发明中进行的两步蚀刻工艺来制造锥形的L形间隔件型材。 根据本发明的目的，已经实现了形成氮化硅侧壁间隔物的新方法。 设置在半导体衬底上的隔离区域。 导电迹线被覆盖在绝缘体层上。 衬底氧化层沉积在导电迹线和绝缘体层上。 沉积覆盖衬垫氧化物层的氮化硅层。 氮化硅层被各向异性地向下蚀刻以减小氮化硅层的垂直厚度，同时不暴露下面的衬里氧化物层。 蚀刻氮化硅层以形成邻近导电迹线的氮化硅侧壁间隔物。 该蚀刻导致锥形的L形侧壁轮廓，并且集成电路器件完成。
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2.发明授权High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness 失效高选择性氮化物间隔物蚀刻，间隔物宽度与沉积的氮化物厚度的高比率公开(公告)号：US06277700B1
公开(公告)日：2001-08-21
申请号：US09480272
申请日：2000-01-11
IPC分类号： H01L21336
CPC分类号： H01L21/31116
摘要： A method of etching silicon nitride spacers beside a gate structure comprising: providing a gate electrode over a gate oxide layer on a substrate. A liner oxide layer is provided over the substrate and the gate electrode. A silicon nitride layer is provided over the liner oxide layer. The invention's nitride etch recipe is performed in a plasma etcher to anisotropically etch the silicon nitride layer to create spacers. The nitride etch recipe comprises a main etch step and an over etch step. The main etch step comprises the following conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, a backside He pressure between 4 and 10 torr; and a HBr flow between 7.5 and 12.5 molar %; a pressure between 400 to 900 mTorr; at a power between 300 and 600 Watts. The etch recipe provides a spacer width to nitride layer thickness ratio of about 1:1 and does not pit the Si substrate surface.
摘要翻译： 一种在栅极结构旁边蚀刻氮化硅间隔物的方法，包括：在衬底上的栅氧化层上提供栅电极。 衬底氧化物层设置在衬底和栅电极之上。 在衬垫氧化物层上提供氮化硅层。 本发明的氮化物蚀刻配方在等离子体蚀刻器中进行，以各向异性地蚀刻氮化硅层以产生间隔物。 氮化物蚀刻配方包括主蚀刻步骤和过蚀刻步骤。 主蚀刻步骤包括以下条件：在35和55摩尔％之间的Cl 2流动，He流动在35和55摩尔％之间，背面He压力在4和10托之间; 7.5至12.5摩尔％的HBr流量; 压力在400至900 mTorr之间; 功率在300至600瓦之间。 蚀刻配方提供了约1：1的间隔物宽度与氮化物层厚度比，并且不会沉积Si衬底表面。
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公开(公告)号：US06316304B1
公开(公告)日：2001-11-13
申请号：US09614553
申请日：2000-07-12
IPC分类号： H01L218238
CPC分类号： H01L21/8238 , H01L21/823468
摘要： A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.
摘要翻译： 描述了形成具有不同宽度的栅极侧壁间隔物的方法。 间隔宽度的变化允许通过改变轻掺杂源极/漏极延伸部分的尺寸来优化MOSFET特性。 该方法使用其中通过常规技术在衬底上形成包括栅电极和栅极氧化物的栅极结构的方法来实现。 轻掺杂的源极漏极延伸部被注入到不被栅极结构保护的衬底中。 然后用绝缘衬垫层覆盖暴露的衬底和栅极结构。 之后是绝缘衬垫层上的蚀刻停止层沉积。 然后在蚀刻停止层上沉积第一间隔氧化物层。 掩蔽需要较厚间隔物的区域，并且去除未掩蔽的间隔氧化物层。 然后剥去掩模，并在整个表面上生长附加的间隔氧化物。 结果是在先前蚀刻步骤期间由掩模保护的区域中较厚的氧化物。 氧化物被各向异性蚀刻，并且沿着栅极侧壁形成间隔物。 在具有较厚氧化物的区域中，间隔物较宽。 该过程通过蚀刻不被间隔物保护的蚀刻停止层而继续。 然后通过将离子注入到不被栅极结构和侧壁间隔物保护的衬底中来形成源极和漏极。 通过调整蚀刻停止层和间隔氧化物层的总厚度来实现间隔物宽度的调整。 通过改变第一间隔氧化物层的沉积厚度来控制间隔宽度变化。
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4.发明授权公开(公告)号：US06294480B1
公开(公告)日：2001-09-25
申请号：US09443427
申请日：1999-11-19
IPC分类号： H01L2131
CPC分类号： H01L29/6653 , H01L21/31116 , H01L21/31144 , H01L29/6659
摘要： A method for forming an L-shaped spacer using a sacrificial organic top coating. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiment, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer.
摘要翻译： 一种使用牺牲有机顶涂层形成L形间隔件的方法。 提供其上具有栅极结构的半导体结构。 在栅极结构上形成衬里氧化物层。 介电间隔层形成在衬垫氧化物层上。 在优选实施例中，电介质间隔层包括氮化硅层或氮氧化硅层。 在电介质间隔层上形成牺牲有机层。 牺牲有机层和电介质间隔层被各向异性蚀刻以形成包括三角形牺牲有机结构和L形介电间隔物的间隔物。 去除三角形牺牲有机结构留下L形介电隔离物。
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5.发明授权Self-aligned floating gate for memory application using shallow trench isolation 有权用于使用浅沟槽隔离的存储器应用的自对准浮动栅极公开(公告)号：US06228713B1
公开(公告)日：2001-05-08
申请号：US09342035
申请日：1999-06-28
IPC分类号： H01H21336
CPC分类号： H01L27/11521 , H01L21/76224
摘要： A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.
摘要翻译： 一种在存储器件中制作自对准浮动栅极的方法。 该方法使用用于浅沟槽隔离（STI）的沟槽蚀刻对浮栅（FG）进行图案化。 因为浮动栅极（FG）与凸起的STI相邻，所以在FG和CG之间消除了尖角，从而增加了栅间电介质层的有效性。 该方法包括：在衬底上形成第一介质层（栅极氧化物）和多晶硅层，蚀刻通过第一电介质氧化物层和多晶硅层并进入衬底以形成沟槽。 剩余的第一电介质层和多晶硅层用作隧道电介质层和浮栅。 沟槽填充有隔离层。 去除掩模层。 在浮栅和隔离层上形成隔间电介质层和控制栅极。
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公开(公告)号：US06211008B1
公开(公告)日：2001-04-03
申请号：US09528241
申请日：2000-03-17
IPC分类号： H01L218242
CPC分类号： H01L28/91
摘要： A method for fabricating a high-density high-capacity capacitor is described. A dielectric layer is provided overlying a semiconductor substrate. A sacrificial layer is deposited overlying the dielectric layer and patterned to form a pattern having a large surface area within a small area on the substrate. In one alternative, spacers are formed on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. A bottom capacitor plate layer is conformally deposited overlying the spacers. In a second alternative, a bottom capacitor plate layer is deposited overlying the patterned sacrificial layer and etched to leave spacers on sidewalls of the patterned sacrificial layer. Thereafter, the sacrificial layer is removed. In both alternatives, a capacitor dielectric layer is deposited overlying the bottom capacitor plate layer. A top capacitor plate layer is deposited overlying the capacitor dielectric layer and patterned to complete fabrication of a high-density high-capacity capacitor.
摘要翻译： 对高密度大容量电容器的制造方法进行说明。 提供覆盖在半导体衬底上的电介质层。 牺牲层沉积在电介质层上并被图案化以形成在衬底上的小区域内具有大表面积的图案。 在一个替代方案中，间隔物形成在图案化牺牲层的侧壁上。 此后，除去牺牲层。 底部电容器平板层被共形地沉积在隔离物上。 在第二替代方案中，沉积底部电容器板层，覆盖图案化的牺牲层并被蚀刻以在图案化牺牲层的侧壁上留下间隔物。 此后，除去牺牲层。 在两种替代方案中，电容器电介质层沉积在底部电容器板层上。 沉积在电容器电介质层上的顶部电容器平板层被图案化以完成高密度大容量电容器的制造。
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7.发明授权Method for forming a lightly doped source and drain structure using an L-shaped spacer 有权使用L形间隔物形成轻掺杂源极和漏极结构的方法
公开(公告)号：US6156598A
公开(公告)日：2000-12-05
申请号：US460113
申请日：1999-12-13
IPC分类号： H01L21/265 , H01L21/311 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66598 , H01L21/2652 , H01L21/31144 , H01L21/823814 , H01L21/823864 , H01L29/6659
摘要： A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyond the L-shaped spacer. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiments, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer. Impurity ions are implanted into the surface of the semiconductor structure forming lightly doped source and drain extensions where the ions are implanted through the L-shaped spacer, and forming source and drain regions beyond the L-shaped spacer where the ions are implanted without passing through the L-shaped spacer.
摘要翻译： 使用牺牲有机顶涂层形成L形间隔物的方法，然后使用L形间隔物同时将轻掺杂的源极和漏极延伸部注入L型间隔物，同时将源极和漏极区域注入超过L形间隔物 。 提供其上具有栅极结构的半导体结构。 在栅极结构上形成衬里氧化物层。 介电间隔层形成在衬垫氧化物层上。 在优选实施例中，电介质间隔层包括氮化硅层或氮氧化硅层。 在电介质间隔层上形成牺牲有机层。 牺牲有机层和电介质间隔层被各向异性蚀刻以形成包括三角形牺牲有机结构和L形介电间隔物的间隔物。 去除三角形牺牲有机结构留下L形介电隔离物。 将杂质离子注入到形成轻掺杂源极和漏极延伸部分的半导体结构的表面中，其中离子通过L形间隔物注入，并且形成超过L形间隔物的源极和漏极区域，其中离子被注入而不通过 L形间隔物。
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8.发明授权Gas-phase additives for an enhancement of lateral etch component during high density plasma film deposition to improve film gap-fill capability 失效用于在高密度等离子体膜沉积期间增强横向蚀刻成分以提高膜间隙填充能力的气相添加剂公开(公告)号：US06355581B1
公开(公告)日：2002-03-12
申请号：US09511276
申请日：2000-02-23
IPC分类号： H01L21316
CPC分类号： H01L21/02274 , C23C16/045 , C23C16/401 , H01L21/02126 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/02211 , H01L21/31612 , H01L21/31625 , H01L21/31629
摘要： A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.
摘要翻译： 一种使用硅烷或无机或有机硅烷衍生物作为硅源的高密度等离子体CVD制备低温氧化硅和硅玻璃层的方法，含有硼，磷和氟的无机化合物作为掺杂化合物，氧和 描述了气体添加剂。 在反应器室中的整个沉积步骤中保持具有一定等离子体密度的RF等离子体。 本发明方法的主要特征是硅源与气体添加剂的摩尔比，其依赖于使用的化合物和沉积工艺条件而保持。 使用无机卤化物作为气体添加剂。 该特征提供了允许膜沉积的适当反应性能的反应条件。 良好的薄膜完整性和在设备结构的步骤内无空隙间隙填充。
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9.发明授权Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer 有权仅使用一个氮化硅层形成侧壁间隔物和硅化物阻挡形状的方法公开(公告)号：US06277683B1
公开(公告)日：2001-08-21
申请号：US09514900
申请日：2000-02-28
IPC分类号： H01L218238
CPC分类号： H01L29/6653 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900° C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.
摘要翻译： 在相同的半导体衬底上形成水化CMOS器件和非硅化物半导体器件的方法，其仅使用一个氮化硅层来提供用于复合间隔物的部件用于在水化CMOS器件的侧面，并提供阻挡形状 在金属硅化物形成期间，对于非水银CMOS器件，已经开发出来。 该方法的特征在于，对于所有CMOS器件，在多晶硅栅极结构的侧面上使用用于限定重掺杂源极/漏极区域的一次性有机间隔物。 然后在800至900℃的温度下通过LPCVD方法获得的氮化硅层被沉积和图案化以在经历自对准硅化物工艺的CMOS器件的侧面上提供所需的间隔物，而同一氮化硅层 用于提供防止非水银CMOS器件形成金属硅化所需的阻挡形状。
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公开(公告)号：US09442609B2
公开(公告)日：2016-09-13
申请号：US13588612
申请日：2012-08-17
申请人： Jie Yu , James Zhang
发明人： Jie Yu , James Zhang
CPC分类号： G06F3/044 , G06F3/0416
摘要： A sensing method is used for a capacitive sensing device, wherein the capacitive sensing device has a plurality of capacitive sensing components, each of which is charged or discharged by a charging component respectively. The sensing method comprises the steps of: a first sampling step of sampling at least one of charging or discharging time of a capacitive sensing component of the plurality of capacitive sensing components to determine a first sample time for the component sampled, wherein the component sampled and at least one another component of the plurality of capacitive sensing components are charged or discharged simultaneously during the first sampling step; a first comparing step of comparing the first sample time for the component sampled with a reference time; and an outputting step of outputting a trigger signal in the event that the first sample time exceeds the reference time.
摘要翻译： 感测方法用于电容感测装置，其中电容性感测装置具有多个电容感测部件，每个电容感测部件分别由充电部件充电或放电。 感测方法包括以下步骤：第一采样步骤，对多个电容感测组件的电容感测组件的充电或放电时间中的至少一个进行采样，以确定采样组件的第一采样时间， 所述多个电容感测部件中的至少另一个部件在所述第一采样步骤期间同时充电或放电; 第一比较步骤，用于将采样的分量的第一采样时间与参考时间进行比较; 以及在第一采样时间超过基准时间的情况下输出触发信号的输出步骤。
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