-
公开(公告)号：US20250048732A1
公开(公告)日：2025-02-06
申请号：US18263540
申请日：2023-06-05
Inventor： Bichan ZHAO , Fen LONG
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
Abstract: The disclosure provides a display panel and a preparation method thereof. The display panel includes an array substrate and an opposite substrate. The array substrate includes a first substrate, a common electrode layer, a first metal layer, a second substrate, and a light-shielding layer. The common electrode layer includes a common electrode, a first electrode, and a groove, and the groove is disposed between the common electrode and the first electrode. The light-shielding layer includes a light-shielding part, and an orthographic projection of the light-shielding part on the first substrate covers an orthographic projection of the first electrode on the first substrate, an orthographic projection of the second electrode on the first substrate, and an orthographic projection of the groove on the first substrate.
-
公开(公告)号：US20250015192A1
公开(公告)日：2025-01-09
申请号：US18455285
申请日：2023-08-24
Inventor： Mingjiue YU , Shimin GE
IPC: H01L29/786 , H01L27/12
Abstract: A thin film transistor includes a gate, a source, a drain, and an active layer. The active layer includes first and second oxide layers that are stacked, the source and the drain are both disposed at a side of the second oxide layer away from the first oxide layer, the first oxide layer is a crystalline oxide layer, and the second oxide layer is a lanthanide oxide layer. When the gate is disposed at a side of the first oxide layer away from the second oxide layer, an atomic proportion of an indium element in the first oxide layer is greater than that of the second oxide layer; when the gate is disposed at the side of the second oxide layer away from the first oxide layer, the atomic proportion of the indium element in the first oxide layer is less than that of the second oxide layer.
-
公开(公告)号：US20240419037A1
公开(公告)日：2024-12-19
申请号：US18266788
申请日：2023-04-21
Inventor： Qingjuan WANG
IPC: G02F1/1339 , G02F1/1333 , G02F1/1362 , H01L27/12
Abstract: A display panel and a display device are provided. the display panel includes an array substrate and an opposite substrate arranged opposite to each other. A plurality of spacers are provided on a side of the opposite substrate adjacent to the array substrate, and a plurality of dams are provided on a side of the array substrate adjacent to the opposite substrate to prevent ends of the spacers adjacent to the array substrate from sliding, thereby preventing the spacers from scratching an alignment layer on a surface of the array substrate.
-
公开(公告)号：US12158676B2
公开(公告)日：2024-12-03
申请号：US17759369
申请日：2022-06-30
Inventor： Xiaobin Hu
IPC: G02F1/1343 , G02F1/1333 , G02F1/1362
Abstract: The present application provides an array substrate and a display device. By placing a first shielding electrode between the data line and the common electrode arranged opposite to each other, the first shielding electrode is connected to a DC voltage signal, so that a data voltage signal of the data line does not affect a signal of the common electrode. This prevents coupling capacitance between the common electrode and the data line, and prevents poor display quality like screen flickering.
-
公开(公告)号：US12154914B2
公开(公告)日：2024-11-26
申请号：US18176138
申请日：2023-02-28
Inventor： Wei Wu
IPC: G02F1/1333 , G02F1/1343 , H01L27/12
Abstract: Disclosed are a display panel and a display device, wherein the display panel includes an opposing substrate, a liquid crystal layer, and an array substrate, the liquid crystal layer is disposed between the opposing substrate and the array substrate; the array substrate includes a base, a first inorganic film layer and a conductive layer, the first inorganic film layer is disposed on the base and has a refractive index greater than or equal to 1.4 and less than or equal to 1.6, the conductive layer is disposed on the base, and the conductive layer is adjacent to the first inorganic film layer.
-
Patent Agency Ranking
公开(公告)号：US20240379689A1
公开(公告)日：2024-11-14
申请号：US18509379
申请日：2023-11-15
Inventor： Kai WANG
IPC: H01L27/12
Abstract: An array substrate and a display panel are provided. In the array substrate, the cushioning structure is arranged below the second connecting line, the side of the cushioning structure close to the via hole extends beyond the second connecting line, the third connecting line overlaps with the second connecting line and a portion of the cushioning structure that extends beyond the second connecting line, and the third connecting line passes through the via hole to connect the first connecting line, so that the third connecting line can connect the first connecting line and the second connecting line to realize the line turning of the first connecting line, and a border of the array substrate is reduced compared with the double-hole connection method.
-
公开(公告)号：US20240377680A1
公开(公告)日：2024-11-14
申请号：US18228131
申请日：2023-07-31
Inventor： Xueer CAI
IPC: G02F1/1337 , G02F1/1333 , G02F1/1335 , G02F1/1343
Abstract: A liquid crystal display panel includes an array substrate, a color filter substrate, and liquid crystal molecules. The array substrate includes a first alignment layer, and the color filter substrate includes a second alignment layer opposite to the first alignment layer. The liquid crystal display panel has a first region and a second region. In a film thickness direction, a sum of a thickness of the first alignment layer and a thickness of the second alignment layer in the first region is greater than a sum of a thickness of the first alignment layer and a thickness of the second alignment layer in the second region.
-
公开(公告)号：US20240329468A1
公开(公告)日：2024-10-03
申请号：US18523182
申请日：2023-11-29
IPC: G02F1/1343 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/13452 , G02F1/1368 , H01L27/124 , G02F1/134372
Abstract: A display panel and a display terminal are disclosed. display panel. The display panel has a display area and a non-display area on at least one side of the display area. The display panel includes: a first substrate; a first metal layer on the first substrate, the first metal layer including a first metal part disposed in the display area and a second metal part disposed in the non-display area; and a second metal layer on a side of the first metal layer away from the first substrate, the second metal layer including a third metal part in the display area and a fourth metal part in the non-display area.
-
公开(公告)号：US20240321835A1
公开(公告)日：2024-09-26
申请号：US18320982
申请日：2023-05-21
Inventor： Zhengbo CUI
IPC: H01L25/075 , H01L33/62
CPC classification number: H01L25/0753 , H01L33/62
Abstract: A spliced display device is provided. The spliced display device includes a display panel, a light complement module, and a plurality of driver chips. The display panel includes subpanels spliced with each other, and a splice slit is formed between the subpanels. The light complement module is disposed corresponding to the splice slit and covers the splice slit. The light complement module includes a driver board and a plurality of light-emitting units disposed on the driver board. The driver chips are disposed on the driver board. Each of the light-emitting units is provided with a corresponding one driver chip therein, and is electrically connected with the corresponding one driver chip. A light emitting direction of the light complement module is same with a light emitting direction of the display panel.
-
公开(公告)号：US20240315097A1
公开(公告)日：2024-09-19
申请号：US18517305
申请日：2023-11-22
Inventor： Ximan LIU
IPC: H10K59/131
CPC classification number: H10K59/131
Abstract: A display panel includes a first fan-out wire, a second fan-out wire and a third fan-out wire in the fan-out routing area are positioned in different layers to save the space for arranging a fan-out route in a horizontal direction. The second fan-out wire partially overlaps with the first and third fan-out wires. This could further shorten the horizontal distance between the fan-out wires, thereby realizing a narrow frame. Because the second fan-out wire partially overlaps the first and third fan-out wires, respectively, the parasitic capacitance between the fan-out wires is reduced, and thus the data signal interference is reduced.
-
-
-
-
-
-
-
-
-
Search Results
130
records
(took 0.024 seconds)
