公开(公告)号：US09543316B2

公开(公告)日：2017-01-10

申请号：US14668938

申请日：2015-03-25

申请人： Hyunmin Lee ,  Changseok Kang ,  Jongwon Kim ,  Hyeong Park

发明人： Hyunmin Lee ,  Changseok Kang ,  Jongwon Kim ,  Hyeong Park

IPC分类号： H01L27/115 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper.

摘要翻译： 本发明的概念提供半导体存储器件及其制造方法。 堆叠结构和垂直通道结构设置在基板上。 堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。 垂直通道结构穿透堆叠结构。 导电垫设置在垂直通道结构上。 蚀刻停止器覆盖导电焊盘的侧壁。 焊盘触点设置在导电焊盘上以与导电焊盘接触。 焊盘触点进一步与蚀刻停止器接触。

公开(公告)号：US20160293626A1

公开(公告)日：2016-10-06

申请号：US15059993

申请日：2016-03-03

申请人： JONGWON KIM ,  HYEONG PARK ,  HYUNMIN LEE ,  HOJONG KANG ,  JOOWON PARK ,  SEUNGMIN SONG

发明人： JONGWON KIM ,  HYEONG PARK ,  HYUNMIN LEE ,  HOJONG KANG ,  JOOWON PARK ,  SEUNGMIN SONG

IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

摘要： A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

摘要翻译： 半导体存储器件包括堆叠结构，其包括垂直堆叠在衬底上的栅电极和穿过栅电极的垂直沟道部分，连接到垂直沟道部分的位线和连接到堆叠上的栅电极的多条导线 结构体。 导线形成多个堆叠层，并且包括第一导线和第二导线。 从衬底设置在第一电平的第一导电线的数量不同于从衬底设置在第二电平的第二导电线的数量。 第一级与第二级不同。

公开(公告)号：US20160043100A1

公开(公告)日：2016-02-11

申请号：US14668938

申请日：2015-03-25

申请人： Hyunmin LEE ,  CHANGSEOK KANG ,  JONGWON KIM ,  Hyeong PARK

发明人： Hyunmin LEE ,  CHANGSEOK KANG ,  JONGWON KIM ,  Hyeong PARK

IPC分类号： H01L27/115 ,  H01L23/535

CPC分类号： H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper.

摘要翻译： 本发明的概念提供半导体存储器件及其制造方法。 堆叠结构和垂直通道结构设置在基板上。 堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。 垂直通道结构穿透堆叠结构。 导电垫设置在垂直通道结构上。 蚀刻停止器覆盖导电焊盘的侧壁。 焊盘触点设置在导电焊盘上以与导电焊盘接触。 焊盘触点进一步与蚀刻停止器接触。