METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE USING PROBE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME
    1.
    发明申请
    METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE USING PROBE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 审中-公开
    使用探针和半导体存储器件测试半导体存储器件的方法

    公开(公告)号:US20110089964A1

    公开(公告)日:2011-04-21

    申请号:US12980437

    申请日:2010-12-29

    IPC分类号: G01R31/20

    摘要: Example embodiments relate to a semiconductor memory device including a first pad having a probe region and a sensing region, the first pad may be adapted to come in contact with a primary probe, a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit may generate an output current in response to a contact point of the primary probe, and a second pad may be adapted to come in contact with a secondary probe to input/output an electric signal. The output current of the sensing unit may be output through the second pad or the secondary probe.

    摘要翻译: 示例性实施例涉及包括具有探针区域和感测区域的第一焊盘的半导体存储器件,第一焊盘可以适于与主探针接触,感测单元适于感测第一焊盘的弱接触和 主探头,感测单元可以响应于主探针的接触点而产生输出电流,并且第二焊盘可以适于与辅助探针接触以输入/输出电信号。 感测单元的输出电流可以通过第二垫或辅助探针输出。

    Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same
    2.
    发明授权
    Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same 有权
    用于在更宽的电源电压范围内产生稳定的升压电压的升压电压产生电路和具有该升压电压的半导体存储器件

    公开(公告)号:US07501881B2

    公开(公告)日:2009-03-10

    申请号:US11707001

    申请日:2007-02-16

    IPC分类号: G05F1/10

    摘要: The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease. Accordingly, the boosting voltage generating circuit of example embodiments may generate a stable boosting voltage under a wider range of supply voltage.

    摘要翻译: 示例性实施例的升压电压产生电路可以包括升压电平检测单元,第一增压泵和第二增压泵。 升压电平检测单元可以被配置为产生目标电平检测信号和余量电平检测信号。 与目标电压电平相比,目标电平检测信号可以根据升压电压的电平具有逻辑状态,并且边沿电平检测信号可以根据升压电压的电平与余量电压电平相比具有逻辑状态 ,余量电压电平高于目标电压电平。 可以基于目标电压电平来控制第一增压泵。 可以基于余量电压电平来控制第二增压泵。 根据示例性实施例的升压电压产生电路,第二增压泵的升压电压的过冲可能显着降低。 因此,示例性实施例的升压电压产生电路可以在更宽的电源电压范围内产生稳定的升压电压。

    Method for testing semiconductor memory device using probe and semiconductor memory device using the same
    3.
    发明申请
    Method for testing semiconductor memory device using probe and semiconductor memory device using the same 失效
    使用探针和半导体存储器件的半导体存储器件的测试方法

    公开(公告)号:US20080164897A1

    公开(公告)日:2008-07-10

    申请号:US12003899

    申请日:2008-01-03

    IPC分类号: G01R31/26

    摘要: Example embodiments relate to a semiconductor memory device including a first pad having a probe region and a sensing region, the first pad may be adapted to come in contact with a primary probe, a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit may generate an output current in response to a contact point of the primary probe, and a second pad may be adapted to come in contact with a secondary probe to input/output an electric signal. The output current of the sensing unit may be output through the second pad or the secondary probe.

    摘要翻译: 示例性实施例涉及包括具有探针区域和感测区域的第一焊盘的半导体存储器件,第一焊盘可以适于与主探针接触,感测单元适于感测第一焊盘的弱接触和 主探头,感测单元可以响应于主探针的接触点而产生输出电流,并且第二焊盘可以适于与辅助探针接触以输入/输出电信号。 感测单元的输出电流可以通过第二垫或辅助探针输出。

    Method for testing semiconductor memory device using probe and semiconductor memory device using the same
    4.
    发明授权
    Method for testing semiconductor memory device using probe and semiconductor memory device using the same 失效
    使用探针和半导体存储器件的半导体存储器件的测试方法

    公开(公告)号:US07863914B2

    公开(公告)日:2011-01-04

    申请号:US12003899

    申请日:2008-01-03

    IPC分类号: G01R31/02

    摘要: Example embodiments relate to a semiconductor memory device including a first pad having a probe region and a sensing region, the first pad may be adapted to come in contact with a primary probe, a sensing unit adapted to sense a weak contact of the first pad and the primary probe, the sensing unit may generate an output current in response to a contact point of the primary probe, and a second pad may be adapted to come in contact with a secondary probe to input/output an electric signal. The output current of the sensing unit may be output through the second pad or the secondary probe.

    摘要翻译: 示例性实施例涉及包括具有探针区域和感测区域的第一焊盘的半导体存储器件,第一焊盘可以适于与主探针接触,感测单元适于感测第一焊盘的弱接触和 主探头,感测单元可以响应于主探针的接触点而产生输出电流,并且第二焊盘可以适于与辅助探针接触以输入/输出电信号。 感测单元的输出电流可以通过第二垫或辅助探针输出。

    Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same
    5.
    发明申请
    Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same 有权
    用于在更宽的电源电压范围内产生稳定的升压电压的升压电压产生电路和具有该升压电压的半导体存储器件

    公开(公告)号:US20070222500A1

    公开(公告)日:2007-09-27

    申请号:US11707001

    申请日:2007-02-16

    IPC分类号: G05F1/10

    摘要: The boosting voltage generating circuit of example embodiments may include a boosting level detection unit, a first boosting pump, and a second boosting pump. The boosting level detection unit may be configured to generate a target level detection signal and a margin level detection signal. The target level detection signal may have a logic state according to a level of a boosting voltage compared with a target voltage level, and the margin level detection signal may have a logic state according to a level of the boosting voltage compared with a margin voltage level, the margin voltage level being higher than the target voltage level. The first boosting pump may be controlled based on a target voltage level. The second boosting pump may be controlled based on a margin voltage level. According to the boosting voltage generating circuit of example embodiments, overshoot of the boosting voltage by the second boosting pump may remarkably decrease. Accordingly, the boosting voltage generating circuit of example embodiments may generate a stable boosting voltage under a wider range of supply voltage.

    摘要翻译: 示例性实施例的升压电压产生电路可以包括升压电平检测单元,第一增压泵和第二增压泵。 升压电平检测单元可以被配置为产生目标电平检测信号和余量电平检测信号。 与目标电压电平相比,目标电平检测信号可以根据升压电压的电平具有逻辑状态,并且边沿电平检测信号可以根据升压电压的电平与余量电压电平相比具有逻辑状态 ,余量电压电平高于目标电压电平。 可以基于目标电压电平来控制第一增压泵。 可以基于余量电压电平来控制第二增压泵。 根据示例性实施例的升压电压产生电路,第二增压泵的升压电压的过冲可能显着降低。 因此,示例性实施例的升压电压产生电路可以在更宽的电源电压范围内产生稳定的升压电压。