公开(公告)号：US08677166B2

公开(公告)日：2014-03-18

申请号：US13084924

申请日：2011-04-12

申请人： Heon-Hee Lee ,  Hoi-Jin Lee

发明人： Heon-Hee Lee ,  Hoi-Jin Lee

IPC分类号： G06F1/00 ,  H03L5/00

CPC分类号： H03K19/0013 ,  H03K19/00361 ,  H03K19/01721

摘要： A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.

摘要翻译： 半导体器件包括电源门控单元，组合逻辑单元和夹紧单元。 电源门控单元导通，根据输入信号在输出电极输出内部信号，或根据操作模式关闭。 组合逻辑单元包括通过数据线直接连接到电力门控单元的输出电极的输入电极，并且基于通过数据线接收的内部信号产生输出信号。 夹紧单元导通，根据操作模式将内部信号钳位在逻辑高电平或逻辑低电平或关闭。 半导体器件夹紧功率选通单元的输出电极，而不会降低半导体器件的操作速度。

公开(公告)号：US08779828B2

公开(公告)日：2014-07-15

申请号：US13417531

申请日：2012-03-12

申请人： Heon-hee Lee ,  Hoi-jin Lee ,  Taek-kyun Shin

发明人： Heon-hee Lee ,  Hoi-jin Lee ,  Taek-kyun Shin

IPC分类号： H03L5/00

CPC分类号： H03K19/017509

摘要： A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.

摘要翻译： 一种半导体器件，包括在具有第一范围的第一操作电压下工作并用于产生数据信号的第一功能块，在具有第二范围的第二操作电压下操作的第二功能块，以及用于执行或不执行的电压电平控制单元 根据第一操作电压和第二操作电压之间的差的存在或不存在，对数据信号的电压电平执行电平移位操作，并且将电平移位数据信号或数据信号发送到 第二功能块。

公开(公告)号：US20130305078A1

公开(公告)日：2013-11-14

申请号：US13734176

申请日：2013-01-04

申请人： Heon-Hee Lee ,  Hoi Jin Lee ,  Jeong Lae Cho

发明人： Heon-Hee Lee ,  Hoi Jin Lee ,  Jeong Lae Cho

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： A data processing system, comprising: a PLL configured to receive a reference clock and to generate a common clock; a processing unit configured to output an operation condition data based on one of temperature, voltage, or process information; and at least two data processing circuits, each comprising: a first clock signal generator configured to receive the common clock signal, the first clock signal generator having a first clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data; and a second clock signal generator configured to receive the common clock signal, the second clock signal generator having a second clock latency adjusting circuit configured to adjust clock signal propagation delay based on the operation condition data.

摘要翻译： 一种数据处理系统，包括：被配置为接收参考时钟并产生公共时钟的PLL; 处理单元，被配置为基于温度，电压或处理信息之一输出操作条件数据; 以及至少两个数据处理电路，每个数据处理电路包括：第一时钟信号发生器，被配置为接收所述公共时钟信号，所述第一时钟信号发生器具有第一时钟延迟调整电路，其被配置为基于所述操作条件数据来调整时钟信号传播延迟; 以及第二时钟信号发生器，被配置为接收所述公共时钟信号，所述第二时钟信号发生器具有被配置为基于所述操作条件数据来调整时钟信号传播延迟的第二时钟延迟调整电路。

公开(公告)号：US20120249211A1

公开(公告)日：2012-10-04

申请号：US13417531

申请日：2012-03-12

申请人： Heon-hee LEE ,  Hoi-jin LEE ,  Taek-kyun SHIN

发明人： Heon-hee LEE ,  Hoi-jin LEE ,  Taek-kyun SHIN

IPC分类号： H03L5/00

CPC分类号： H03K19/017509

摘要： A semiconductor device including a first function block operating at a first operation voltage having a first range and for generating a data signal, a second function block operating at a second operation voltage having a second range, and a voltage level control unit for performing or not performing a level shifting operation on a voltage level of the data signal depending on the existence or non-existence of a difference between the first operation voltage and the second operation voltage, and for transmitting a level-shifted data signal or the data signal to the second function block.

摘要翻译： 一种半导体器件，包括在具有第一范围的第一操作电压下工作并用于产生数据信号的第一功能块，在具有第二范围的第二操作电压下操作的第二功能块，以及用于执行或不执行的电压电平控制单元 根据第一操作电压和第二操作电压之间的差的存在或不存在，对数据信号的电压电平执行电平移位操作，并且将电平移位数据信号或数据信号发送到 第二功能块。

公开(公告)号：US20110289369A1

公开(公告)日：2011-11-24

申请号：US13098749

申请日：2011-05-02

申请人： Heon-Hee LEE ,  Hoi Jin LEE

发明人： Heon-Hee LEE ,  Hoi Jin LEE

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547

摘要： An integrated circuit for performing a design for testability (DFT) scan test is provided. The integrated circuit includes at least one scan chain including a plurality of flip-flops, at least one interface scan chain including a plurality of flip-flops, a decompressor configured to be connected with an input terminal of the at least one interface scan chain and to decompress a first input signal and then transmit it to the at least one scan chain, a compressor configured to be connected with an output terminal of the at least one scan chain and to compress an output signal of the at least one scan chain, and at least one multiplexer configured to be connected with the decompressor and to selectively output an output signal of the decompressor or a second input signal in response to a control signal.

摘要翻译： 提供了用于执行可测性（DFT）扫描测试设计的集成电路。 所述集成电路包括至少一个包括多个触发器的扫描链，包括多个触发器的至少一个接口扫描链，被配置为与所述至少一个接口扫描链的输入端连接的解压缩器，以及 解压缩第一输入信号，然后将其发送到所述至少一个扫描链，所述压缩器被配置为与所述至少一个扫描链的输出端连接并且压缩所述至少一个扫描链的输出信号，以及 至少一个多路复用器，被配置为与解压缩器连接，并且响应于控制信号选择性地输出解压缩器的输出信号或第二输入信号。

公开(公告)号：US08539293B2

公开(公告)日：2013-09-17

申请号：US13098749

申请日：2011-05-02

申请人： Heon-Hee Lee ,  Hoi Jin Lee

发明人： Heon-Hee Lee ,  Hoi Jin Lee

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： An integrated circuit for performing a design for testability (DFT) scan test is provided. The integrated circuit includes at least one scan chain including a plurality of flip-flops, at least one interface scan chain including a plurality of flip-flops, a decompressor configured to be connected with an input terminal of the at least one interface scan chain and to decompress a first input signal and then transmit it to the at least one scan chain, a compressor configured to be connected with an output terminal of the at least one scan chain and to compress an output signal of the at least one scan chain, and at least one multiplexer configured to be connected with the decompressor and to selectively output an output signal of the decompressor or a second input signal in response to a control signal.

摘要翻译： 提供了用于执行可测性（DFT）扫描测试设计的集成电路。 所述集成电路包括至少一个包括多个触发器的扫描链，包括多个触发器的至少一个接口扫描链，被配置为与所述至少一个接口扫描链的输入端连接的解压缩器，以及 解压缩第一输入信号，然后将其发送到所述至少一个扫描链，所述压缩器被配置为与所述至少一个扫描链的输出端连接并且压缩所述至少一个扫描链的输出信号，以及 至少一个多路复用器，被配置为与解压缩器连接，并且响应于控制信号选择性地输出解压缩器的输出信号或第二输入信号。

公开(公告)号：US20110320843A1

公开(公告)日：2011-12-29

申请号：US13084924

申请日：2011-04-12

申请人： Heon-Hee Lee ,  Hoi-Jin Lee

发明人： Heon-Hee Lee ,  Hoi-Jin Lee

IPC分类号： G06F1/26

CPC分类号： H03K19/0013 ,  H03K19/00361 ,  H03K19/01721

摘要： A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.

摘要翻译： 半导体器件包括电源门控单元，组合逻辑单元和夹紧单元。 电源门控单元导通，根据输入信号在输出电极输出内部信号，或根据操作模式关闭。 组合逻辑单元包括通过数据线直接连接到电力门控单元的输出电极的输入电极，并且基于通过数据线接收的内部信号产生输出信号。 夹紧单元导通，根据操作模式将内部信号钳位在逻辑高电平或逻辑低电平或关闭。 半导体器件夹紧功率选通单元的输出电极，而不会降低半导体器件的操作速度。