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1.发明授权
公开(公告)号：US5408476A
公开(公告)日：1995-04-18
申请号：US16871
申请日：1993-02-11
申请人： Masaaki Kawai , Masayoshi Sekido , Yuji Takizawa , Hidetoshi Naito , Satomi Ikeda , Kazuyuki Tajima , Haruo Yamashita , Hideo Tatsuno
发明人： Masaaki Kawai , Masayoshi Sekido , Yuji Takizawa , Hidetoshi Naito , Satomi Ikeda , Kazuyuki Tajima , Haruo Yamashita , Hideo Tatsuno
CPC分类号： H03M13/151 , H03M13/09
摘要： A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.
摘要翻译： 提供了一种基于CRC计算的1位纠错电路，其具有确定m位的输入并行数据并且已经从n个m位串行数据转换的校正子生成电路。 1位错误检测电路循环地将余数提供给余数计算电路，并解码从该循环电源获得的余数数据，并检测1位错误。 实际数据再现电路计算校正子产生电路的第1个差分第n个寄存器的预定寄存器的输出数据与提供给预定寄存器的数据的异或，并获得作为实际数据的并行数据。 一种校正电路，其计算从实际数据再现电路获得的并行数据的异或和由1位错误检测电路检测的1位错误数据，并输出校正数据。
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公开(公告)号：US5469428A
公开(公告)日：1995-11-21
申请号：US858364
申请日：1992-03-25
IPC分类号： H04L12/437 , H04Q11/04 , H04L12/42
CPC分类号： H04L12/437 , H04J2203/006 , H04J2203/0089
摘要： A loop-back recovery technique used when a failure takes place in a ring network, for transmitting information to a path indicated with a path ID number or the time slot position from a periodic frame. This is achieved by establishing working paths on one of the dual ring line between a transmission node and a receiving node thereof, establishing ring-formed protection paths in a ring line of the direction opposite to the working line, and making a loop-back from the working paths to the corresponding protection paths at a node which detected the failure. The receiving node multiplexes the working and protection paths to receive data from either.
摘要翻译： 当在环形网络中发生故障时使用的环回恢复技术，用于将信息发送到由周期性帧中的路径ID号或时隙位置指示的路径。 这通过在传输节点和其接收节点之间的双环线之一上建立工作路径来实现，在与工作线相反的方向的环线中建立环形保护路径，并且从 在检测到故障的节点处的相应保护路径的工作路径。 接收节点多路复用工作和保护路径以接收数据。
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公开(公告)号：US5400329A
公开(公告)日：1995-03-21
申请号：US51900
申请日：1993-04-27
申请人： Nobuyuki Tokura , Yoshio Kajiyama , Hideo Tatsuno
发明人： Nobuyuki Tokura , Yoshio Kajiyama , Hideo Tatsuno
CPC分类号： H04L12/5602 , H04L2012/5636
摘要： Packet transfer is controlled by using an acceleration rate of packet transfers or by using a packet transfer rate acceleration ratio to predict that congestion will occur at a prescribed time in the future. Congestion avoidance in packet integrated networks is thereby achieved in a network having both variable rate terminal nodes and fixed rate terminal nodes. A future packet transfer rate is predicted in a congestion prediction circuit on the basis of a pre-established upper limit for the packet transfer acceleration or acceleration ratio. When it is predicted that the packet transfer rate will exceed a permissible value, a congestion prediction signal is output or a rate increase request indication is deleted. The invention prevents packets from being discarded in the packet network, allows buffer memory capacity of nodes in the network to be decreased, and avoids the generation of new packets when signal congestion is predicted.
摘要翻译： 通过使用分组传送的加速率或通过使用分组传输速率加速比来预测在将来的规定时间内将发生拥塞的分组传送。 因此，在具有可变速率终端节点和固定速率终端节点的网络中实现了分组集成网络中的拥塞避免。 基于分组传送加速度或加速比的预先建立的上限，在拥塞预测电路中预测未来的分组传送速率。 当预测分组传输速率将超过允许值时，输出拥塞预测信号或者删除速率增加请求指示。 本发明防止分组网络中的分组被丢弃，允许减少网络节点的缓冲存储器容量，避免在预测信号拥塞时产生新的分组。
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