公开(公告)号：US5408476A

公开(公告)日：1995-04-18

申请号：US16871

申请日：1993-02-11

申请人： Masaaki Kawai ,  Masayoshi Sekido ,  Yuji Takizawa ,  Hidetoshi Naito ,  Satomi Ikeda ,  Kazuyuki Tajima ,  Haruo Yamashita ,  Hideo Tatsuno

发明人： Masaaki Kawai ,  Masayoshi Sekido ,  Yuji Takizawa ,  Hidetoshi Naito ,  Satomi Ikeda ,  Kazuyuki Tajima ,  Haruo Yamashita ,  Hideo Tatsuno

IPC分类号： H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H04L1/00 ,  G06F11/10

CPC分类号： H03M13/151 ,  H03M13/09

摘要： A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

摘要翻译： 提供了一种基于CRC计算的1位纠错电路，其具有确定m位的输入并行数据并且已经从n个m位串行数据转换的校正子生成电路。 1位错误检测电路循环地将余数提供给余数计算电路，并解码从该循环电源获得的余数数据，并检测1位错误。 实际数据再现电路计算校正子产生电路的第1个差分第n个寄存器的预定寄存器的输出数据与提供给预定寄存器的数据的异或，并获得作为实际数据的并行数据。 一种校正电路，其计算从实际数据再现电路获得的并行数据的异或和由1位错误检测电路检测的1位错误数据，并输出校正数据。

公开(公告)号：US5515386A

公开(公告)日：1996-05-07

申请号：US311727

申请日：1994-09-23

申请人： Yuji Takizawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Kazuyuki Tajima ,  Satomi Ikeda

发明人： Yuji Takizawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Kazuyuki Tajima ,  Satomi Ikeda

IPC分类号： H04L12/951 ,  H04Q11/04 ,  G06F11/00

CPC分类号： H04Q11/0478 ,  H04L49/40 ,  H04L2012/5616 ,  H04L2012/5646 ,  H04L49/557

摘要： A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern. The transmission circuit includes a first output circuit for outputting the normal cell data, an error correcting code generator for generating the second data based on the first data of the normal cell data supplied from the first output circuit, a second output circuit for outputting the first and second data of the idle cell data, a scrambler for scrambling the third data of the normal cell data supplied from the first output circuit, and a selector for selecting one of the first output circuit, the error correcting code generator, the second output circuit and the scrambler in accordance with a predetermined order, so that the normal cell data and the idle cell data are output from the selector.

摘要翻译： 发送电路通过通信线路发送正常小区数据和空闲小区数据。 发送空闲小区数据以填充不存在要发送的正常数据的通信线路中的每个正常小区数据和包括第一数据，第二数据和第三数据的空闲小区数据的时隙。 正常小区数据的第一，第二和第三数据分别表示目的地，第一数据的纠错码和期望信息。 空闲小区数据的第一和第二数据具有预定的比特模式，并且空闲小区数据的第三数据可以具有任何任意的比特模式。 发送电路包括用于输出正常小区数据的第一输出电路，用于根据从第一输出电路提供的正常小区数据的第一数据产生第二数据的纠错码发生器，用于输出第一 和空闲单元数据的第二数据，用于加扰从第一输出电路提供的正常单元数据的第三数据的加扰器，以及用于选择第一输出电路，纠错码产生器，第二输出电路 和加扰器，以便从选择器输出正常小区数据和空闲小区数据。

公开(公告)号：US5257311A

公开(公告)日：1993-10-26

申请号：US876417

申请日：1992-04-30

申请人： Hidetoshi Naito ,  Masaaki Kawai ,  Hisako Watanabe ,  Yuji Takizawa ,  Kazuyuki Tajima ,  Haruo Yamashita

发明人： Hidetoshi Naito ,  Masaaki Kawai ,  Hisako Watanabe ,  Yuji Takizawa ,  Kazuyuki Tajima ,  Haruo Yamashita

IPC分类号： H04Q3/52 ,  H04L12/26 ,  H04L12/70 ,  H04Q3/00 ,  H04Q11/04 ,  H04L9/00

CPC分类号： H04L49/3009 ,  H04L12/2697 ,  H04L43/50 ,  H04L49/3081 ,  H04L49/555 ,  H04Q11/0478 ,  H04L2012/5628 ,  H04L2012/5652 ,  H04L49/30

摘要： A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM cross-connecting apparatus. An initial value of a PN sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and the generated pseudo-noise sequence is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI value in the information field is compared with a VPI value in the header of the test cell when examining the test cell.

公开(公告)号：US5265088A

公开(公告)日：1993-11-23

申请号：US889924

申请日：1992-06-02

申请人： Yuji Takigawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Hisako Watanabe ,  Kazuyuki Tajima ,  Haruo Yamashita

发明人： Yuji Takigawa ,  Masaaki Kawai ,  Hidetoshi Naito ,  Hisako Watanabe ,  Kazuyuki Tajima ,  Haruo Yamashita

IPC分类号： H04L12/70 ,  H04Q11/04 ,  H04J3/26

CPC分类号： H04L49/107 ,  H04L49/3009 ,  H04L49/309 ,  H04L49/555 ,  H04Q11/0478 ,  H04L2012/561 ,  H04L2012/5625 ,  H04L49/30

摘要： A cross-connection apparatus for B-ISDN includes plural interface units, multiplexers, virtual path identifier (VPI) conversion tables, demultiplexers, and loop-back units and a switch unit. The interface unit has a reception port for receiving an ATM cell or inserting a monitor cell, and a transmission port for transferring the ATM cell or extracting the monitor cell; The multiplexer is operatively connected to corresponding interface unit for multiplexing the monitor cell; The VPI conversion tables is operatively connected to corresponding multiplexer for converting the VPI to change a transmission route of the monitor cell; The switch unit is operatively connected to the VPI conversion tables for switching the transmission route of the monitor cell based on the VPI; The demultiplexer is operatively connected to the switch unit for demultiplexing the monitor cell and transferring the monitor cell to the transmission port; The loop-back unit is operatively connected to corresponding interface unit for changing the transmission route so as to transfer the monitor cell to the same interface unit which the monitor cell is inserted, and as a result, the apparatus can be monitored by comparing the inserted monitor cell with the extracted monitor cell in the same interface unit.

公开(公告)号：US4935701A

公开(公告)日：1990-06-19

申请号：US246088

申请日：1988-09-19

申请人： Masaaki Kawai ,  Hisako Watanabe ,  Tomoyuki Ohtsuka ,  Haruo Yamashita

发明人： Masaaki Kawai ,  Hisako Watanabe ,  Tomoyuki Ohtsuka ,  Haruo Yamashita

IPC分类号： H03H11/20

CPC分类号： H03H11/20

摘要： A phase shift circuit used in a regenerating repeater, includes a separating unit for separating an input signal into two separate signals having a phase difference of a phase angle of 90.degree. therebetween, one separated signal having a "0" phase and the other separated signal having a ".pi./2" phase. A distributing unit distributes the "0" phase separated signal and ".pi./2" phase separated signal as three distributed signals having phase difference of phase angles of 90.degree. and 180.degree. therebetween, one distributed signal having a "0" phase and the others being a ".pi./2" phase distributed signal and a ".pi." phase distributed signal. A weighting/compounding unit analyzes the "0" phase distributed signal, ".pi./2" phase distributed signal, and ".pi." phase distributed signal regarding a plurality of phase signals each having a phase shift extent, compounds each of the phase signals after being weighted by each amplitude, the weighting being performed by a weight control signal applied from an external stage, and generates an output signal adding a phase shift proportional to the weight to the input signal.

公开(公告)号：US20090301437A1

公开(公告)日：2009-12-10

申请号：US11913697

申请日：2007-02-07

申请人： Hiroaki Mizoguchi ,  Takahiko Fujiwara ,  Kunihiko Nakata ,  Kenji Sakurai ,  Hiroki Ichinose ,  Masaaki Kawai ,  Atsunori Hirata

发明人： Hiroaki Mizoguchi ,  Takahiko Fujiwara ,  Kunihiko Nakata ,  Kenji Sakurai ,  Hiroki Ichinose ,  Masaaki Kawai ,  Atsunori Hirata

IPC分类号： F02D41/14 ,  F01N3/10

CPC分类号： F01N3/24 ,  F01N3/101 ,  F01N3/2006 ,  F01N2340/00 ,  F01N2430/06 ,  F01N2560/06 ,  F01N2560/14 ,  F02D41/0245 ,  F02D41/025 ,  F02D41/0255 ,  F02D2200/0802 ,  Y02T10/22 ,  Y02T10/26

摘要： The combustion air-fuel ratio is made leaner than the stoichiometric air-fuel ratio at the time of engine startup and the combustion air-fuel ratio is made richer than the stoichiometric air-fuel ratio and the exhaust downstream part of the three-way catalyst apparatus is raised in temperature when it is judged that just the exhaust upstream part of the three-way catalyst apparatus arranged in the engine exhaust system has been raised to the catalyst activation temperature.

摘要翻译： 燃料空燃比比发动机启动时的理论空燃比更稀，燃烧空燃比比化学计量空燃比和三元催化剂的排气下游部分更浓 当判断出排列在发动机排气系统中的三通催化剂装置的排气上游部分刚刚升高到催化剂活化温度时，装置升温。

公开(公告)号：US20090250591A1

公开(公告)日：2009-10-08

申请号：US12382864

申请日：2009-03-25

申请人： Shinji Yamashita ,  Tsuyoshi Yamamoto ,  Masaaki Kawai ,  Hiroyuki Fujita

发明人： Shinji Yamashita ,  Tsuyoshi Yamamoto ,  Masaaki Kawai ,  Hiroyuki Fujita

IPC分类号： G01J1/20

CPC分类号： G02B26/06 ,  G02B26/0841

摘要： An optical wavefront control system by which the number of optical components or costs can be reduced. If an optical wavefront control system comprising an optical wavefront control section for controlling, in accordance with a wavefront control signal for controlling a phase of a wavefront of input light inputted and an aberration control signal for controlling an aberration of the input light inputted, the phase and the aberration and for outputting output light, a detection section for detecting optical information regarding a wavefront and an aberration of the output light inputted from the optical wavefront control section, and a control circuit section for outputting the wavefront control signal and the aberration control signal to the optical wavefront control section on the basis of the optical information detected by the detection section is used, the wavefront of the input light can be controlled and the aberration can be corrected. Accordingly, there is no need to locate another optical component for correcting the aberration.

摘要翻译： 一种光学波前控制系统，可以减少光学部件或成本的数量。 如果光波阵面控制系统包括光波前控制部分，用于根据用于控制输入的输入光的波前的相位的波前控制信号和用于控制输入的输入光的像差的像差控制信号来控制相位 和用于输出输出光的像差，用于检测关于波前的光学信息的检测部分和从光学波前控制部分输入的输出光的像差;以及控制电路部分，用于输出波前控制信号和像差控制信号 使用基于由检测部检测出的光信息到光波前控制部的光波阵面，可以控制输入光的波前，并且可以校正像差。 因此，不需要定位用于校正像差的另一光学部件。

公开(公告)号：US20080187172A1

公开(公告)日：2008-08-07

申请号：US11792084

申请日：2005-12-09

申请人： Nobuyuki Otsu ,  Masaaki Kawai

发明人： Nobuyuki Otsu ,  Masaaki Kawai

IPC分类号： G06K9/00

CPC分类号： G06K9/32 ,  G06K2009/3291 ,  G06T7/20

摘要： A tracing device and a tracing method for realizing a real-time trace of a moving object such as a person from a time-varying image by method of a light processing load, and for learning features through the trace thereby to realize a trace of higher precision. The tracing device divides time-varying data inputted into partial images (in a strip or rectangle shape), and compares the background image containing no tracing object thereby with the current image thereby to extract the divided image having the tracing object. In order to discriminate the tracing object, moreover, the tracing device calculates the color high-level local self-correlated data, from which the features of color and shape can be extracted all at once, and performs the discrimination on the basis of a distance from the featuring data of the tracing object registered. The tracing device updates the background image and the registered featuring data into the latest ones. The features are acquired while tracing the tracing object, and the object is discriminated by utilizing the features so that a strong and highly precise trace can be realized.

摘要翻译： 一种跟踪装置和跟踪方法，用于通过光处理负载的方法实现来自时变图像的人的移动物体的实时轨迹，并且通过轨迹学习特征，从而实现更高的轨迹 精确。 跟踪装置将输入的部分图像（条形或矩形）中的时变数据分割，并将不含跟踪对象的背景图像与当前图像进行比较，从而提取具有跟踪对象的分割图像。 此外，为了区分跟踪对象，跟踪装置计算出可以一次性提取颜色和形状的特征的颜色高级局部自相关数据，并且基于距离进行鉴别 从跟踪对象的特征数据注册。 跟踪设备将背景图像和已注册的特征数据更新为最新的。 在跟踪跟踪对象时获取特征，并且通过利用特征来区分对象，从而可以实现强烈和高精度的跟踪。

公开(公告)号：US5696759A

公开(公告)日：1997-12-09

申请号：US554038

申请日：1995-11-06

申请人： Hiroshi Tomonaga ,  Naoki Matsuoka ,  Masaaki Kawai

发明人： Hiroshi Tomonaga ,  Naoki Matsuoka ,  Masaaki Kawai

IPC分类号： H04Q3/42 ,  H04L12/70 ,  H04L12/813 ,  H04L12/931 ,  H04Q3/00 ,  H04L12/56 ,  H04L12/26

CPC分类号： H04L12/5601 ,  H04L49/3009 ,  H04L49/3081 ,  H04L2012/5619 ,  H04L2012/5625 ,  H04L2012/5636 ,  H04L2012/5639 ,  H04L2012/5647 ,  H04L2012/5672

摘要： A switching equipment accommodates lines and includes a line interface for processing data from the line on the unit of cell. The line interface has a basic processing unit and an additional processing unit. The basic processing unit performs a basic process on the cell. The additional processing unit separated from the basic processing unit but disconnectably connected to the basic processing unit executes an additional process on the cell. The additional processing unit includes a plurality of processing blocks for effecting a plurality of additional processes on the cells. Each processing block is individually disconnectably connected to the basic processing unit. The basic processing unit includes a selecting portion for selecting, when one or more processing blocks within the additional processing unit are connected, the connected processing blocks and performing the additional process on the cell.

摘要翻译： 交换设备容纳线路，并且包括用于处理来自单元单元的线路的数据的线路接口。 线路接口具有基本处理单元和附加处理单元。 基本处理单元对单元执行基本处理。 与基本处理单元分离但与基本处理单元可断开连接的附加处理单元在单元上执行附加处理。 附加处理单元包括用于在单元上进行多个附加处理的多个处理块。 每个处理块单独地可拆卸地连接到基本处理单元。 基本处理单元包括：选择部分，用于当连接附加处理单元内的一个或多个处理块时，选择所连接的处理块并在该单元上执行附加处理。

公开(公告)号：US5001726A

公开(公告)日：1991-03-19

申请号：US313506

申请日：1989-02-22

申请人： Masaaki Kawai ,  Hisako Watanabe ,  Tomoyuki Ohtsuka

发明人： Masaaki Kawai ,  Hisako Watanabe ,  Tomoyuki Ohtsuka

IPC分类号： H03M5/06 ,  G01R19/165 ,  H03K5/08 ,  H04L1/00 ,  H04L25/03

CPC分类号： G01R19/1658 ,  H03K5/086

摘要： A circuit for generating a discrimination voltage level V.sub.ref which is used as a reference voltage to discriminate between two adjacent logic levels or an input signal which can have a plurality of different voltage levels generally corresponding to a plurality of respective, different logic levels. The frequency at which the levels of the input signals lie in the upper half of the vicinity (i.e., the voltage range from the level V.sub.ref -.DELTA.V to the level V.sub.ref +.DELTA.V) of the discrimination voltage level (i.e., the "upper half" thereof being the voltage range from V.sub.ref to V.sub.ref +.DELTA.V, ".DELTA.V" being a predetermined off-set value) and the frequency at which the levels of the input signals lie in the lower half of the vicinity (i.e., as above defined) of the discrimination level (i.e., the "low half" thereof being the voltage range from V.sub.ref -.DELTA.V to V.sub.ref) are compared, and the discrimination level is controlled so that the above two frequencies are the same.