公开(公告)号：US06873830B2

公开(公告)日：2005-03-29

申请号：US09852273

申请日：2001-05-10

申请人： Masayuki Katakura ,  Hideshi Motoyama

发明人： Masayuki Katakura ,  Hideshi Motoyama

IPC分类号： H03F1/30 ,  H03F3/193 ,  H04B1/04

CPC分类号： H03F1/306 ,  H03F2200/372

摘要： A bias circuit according to the present invention includes a monitoring circuit having a second FET and a resistance connected to a drain of the second FET for monitoring a drain current of a first FET to be supplied with a gate bias; a differential circuit including a third FET having a gate supplied with a reference voltage, a fourth FET having a gate connected to the drain of the second FET, sources of the third FET and the fourth FET being connected to a common point, and resistances connected to drains of the third FET and the fourth FET, respectively; and a fifth FET having a drain connected to the common source of the third FET and the fourth FET; wherein a drain voltage of the third FET is fed back to gates of the first FET and the second FET, and a drain voltage of the fourth FET is fed back to a gate of the fifth FET.

摘要翻译： 根据本发明的偏置电路包括具有第二FET的监控电路和连接到第二FET的漏极的电阻，用于监视要被提供栅极偏压的第一FET的漏极电流; 包括具有提供有参考电压的栅极的第三FET的差分电路，具有连接到第二FET的漏极的栅极的第四FET，第三FET和第四FET的源极连接到公共点，并且电阻连接 分别连接到第三FET和第四FET的漏极; 以及第五FET，其漏极连接到第三FET和第四FET的公共源; 其中所述第三FET的漏极电压被反馈到所述第一FET和所述第二FET的栅极，并且所述第四FET的漏极电压被反馈到所述第五FET的栅极。