公开(公告)号：US20070245185A1

公开(公告)日：2007-10-18

申请号：US11727451

申请日：2007-03-27

申请人： Hiroaki Shoda

发明人： Hiroaki Shoda

IPC分类号： G01R31/28

CPC分类号： G01R31/318541

摘要： A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.

摘要翻译： 触发器具有第一锁存器和第二锁存器。 第一锁存器具有基于第一时钟信号的逻辑电平的第一反馈电路和第一选择电路，其选择第一反馈电路的第一数据输入信号和输出信号之一。 第二锁存器具有第二反馈电路和第二选择电路，其在第一锁存器的情况下基于反相逻辑电平选择第一锁存器的输出信号和第二反馈电路的输出信号。 第一反馈电路具有第三选择电路，其基于第二时钟信号的逻辑电平选择第一锁存器的输出信号和第二数据输入信号中的一个，并将由第三选择电路选择的信号输出到第一 选择电路。

公开(公告)号：US07600167B2

公开(公告)日：2009-10-06

申请号：US11727451

申请日：2007-03-27

申请人： Hiroaki Shoda

发明人： Hiroaki Shoda

IPC分类号： G01R31/28 ,  G01R31/26 ,  G06F1/00 ,  G11C29/00 ,  H03K3/289 ,  H03K3/00 ,  H03K5/13 ,  H03H11/16 ,  H03K19/00 ,  H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K3/02

CPC分类号： G01R31/318541

摘要： A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.

摘要翻译： 触发器具有第一锁存器和第二锁存器。 第一锁存器具有基于第一时钟信号的逻辑电平的第一反馈电路和第一选择电路，其选择第一反馈电路的第一数据输入信号和输出信号之一。 第二锁存器具有第二反馈电路和第二选择电路，其在第一锁存器的情况下基于反相逻辑电平选择第一锁存器的输出信号和第二反馈电路的输出信号。 第一反馈电路具有第三选择电路，其基于第二时钟信号的逻辑电平选择第一锁存器的输出信号和第二数据输入信号中的一个，并将由第三选择电路选择的信号输出到第一 选择电路。