公开(公告)号：US5159688A

公开(公告)日：1992-10-27

申请号：US691284

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

公开(公告)号：US5163150A

公开(公告)日：1992-11-10

申请号：US691297

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。 虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

公开(公告)号：US5036458A

公开(公告)日：1991-07-30

申请号：US287622

申请日：1988-12-20

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。 处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。 在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。

公开(公告)号：US5148542A

公开(公告)日：1992-09-15

申请号：US517402

申请日：1990-05-01

申请人： Hajime Sakuma ,  Hiroko Shinohara

发明人： Hajime Sakuma ,  Hiroko Shinohara

IPC分类号： G06F9/48

CPC分类号： G06F9/4881

摘要： An apparatus for processing a plurality of tasks comprises a central processing unit (CPU) equipped with a microprogram memory, and a memory. A processing demand to the real time OS required for the execution of the multitask processing is treated as exclusive instruction. For this purpose, the system includes a decoder for decoding the exclusive instruction, and the CPU or the memory has a microprogram for the realization of the instruction.

摘要翻译： 用于处理多个任务的装置包括配备有微程序存储器和存储器的中央处理单元（CPU）。 对执行多任务处理所需的实时OS的处理要求被视为独占指令。 为此，该系统包括用于解码专用指令的解码器，并且CPU或存储器具有用于实现该指令的微程序。