公开(公告)号：US5241644A

公开(公告)日：1993-08-31

申请号：US728794

申请日：1991-07-08

申请人： Masahiro Nomura ,  Shigetatsu Katori

发明人： Masahiro Nomura ,  Shigetatsu Katori

IPC分类号： G06F5/10 ,  G06F9/38

CPC分类号： G06F5/10 ,  G06F9/3802 ,  G06F9/3814 ,  G06F2205/108

摘要： A queue apparatus comprises a multi-stage queue latch for storing instruction codes or data in a first-in first-out manner; a first queue pointer associated with the queue latch for indicating a read position of an upper half place portion of the instruction codes or data stored in the queue latch and a second queue pointer associated with the queue latch for indicating a reading position of a lower half place portion of the instruction codes or data stored in the queue latch. An exchanger is coupled in order to the queue latch to receive the upper and lower half place portions of the instruction codes or data read out form the queue latch and for selectively exchanging the positions of the received upper and lower half place portions.

摘要翻译： 队列装置包括用于以先进先出方式存储指令代码或数据的多级队列锁存器; 与队列锁存器相关联的用于指示存储在队列锁存器中的指令代码或数据的上半部分的读取位置的第一队列指针和与队列锁存器相关联的第二队列指针，用于指示下半部分的读取位置 存储在队列锁存器中的指令代码或数据的位置部分。 耦合交换器以便队列锁存器接收从队列锁存器读出的指令代码或数据的上半部分和下半部分，并且用于选择性地交换所接收的上半部分和下半部分的位置。

公开(公告)号：US5159688A

公开(公告)日：1992-10-27

申请号：US691284

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

公开(公告)号：US4984190A

公开(公告)日：1991-01-08

申请号：US569539

申请日：1990-08-20

申请人： Shigetatsu Katori ,  Yukio Maehashi ,  Yukari Misawa

发明人： Shigetatsu Katori ,  Yukio Maehashi ,  Yukari Misawa

IPC分类号： G06F13/28 ,  G06F13/42 ,  G06F15/17

CPC分类号： G06F13/423 ,  G06F13/28 ,  G06F15/17

摘要： Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal. When the reception of the serial data on the data line is ended, the output circuit outputs the reception confirmation signal to the data line in synchronism with the first or second signal.

摘要翻译： 这里公开了一种串行数据传输系统，其具有通过单个数据线连接的第一和第二串行数据处理器以及用于在其间传送串行数据的单个时钟线。 第一和第二串行数据处理器中的每一个包括：接收确认信号输出装置，用于向数据线输出接收确认信号; 以及接收确认​​信号检测装置，用于检测数据线上的接收确认信号。 与输出到时钟线的串行时钟脉冲同步执行数据传送的确认。 或者，第一或第二串行数据处理器包括：输出电路，用于向数据线输出接收确认信号; 用于产生指示串行数据的接收结束的第一信号的电路; 用于产生指示所接收的数据的处理结束的第二信号的电路; 以及用于控制所述接收确认信号的输出的电路。 当数据线上的串行数据的接收结束时，输出电路与第一或第二信号同步地向数据线输出接收确认信号。

公开(公告)号：US5367676A

公开(公告)日：1994-11-22

申请号：US944712

申请日：1992-09-11

申请人： Shigetatsu Katori

发明人： Shigetatsu Katori

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/12

CPC分类号： G06F9/4812

摘要： A data processor includes a central processing unit having an execution unit, a program counter for supplying the address of the instruction to be executed and a program status word for holding the execution status of the program, an interrupt request generating means for generating the processing request in asynchronisum with the central processing unit, and interrupt controller receiving the processing request from the interrupt requested generating means and a data memory for storing the processing data. The interrupt request generating means is capable of generating a macro-service request for starting the macro-service processing while saving the contents of the program counter and the program status word. The data memory the control information for starting the macro-service processing and the command information for executing a plurality of macro-service processing. The control information includes a base address for the command information corresponding to the macro-service processing. The interrupt controller response to the macro-service processing request from the interrupt request generating means and outputs a single macro-service request signal to the central processing unit and directly accesses the data memory permitting the central processing unit to operate continuously.

摘要翻译： 数据处理器包括具有执行单元的中央处理单元，用于提供要执行的指令的地址的程序计数器和用于保持程序的执行状态的程序状态字;产生处理请求的中断请求生成单元 与中央处理单元不同步，以及中断控制器接收来自中断请求生成装置的处理请求和用于存储处理数据的数据存储器。 中断请求产生装置能够在保存程序计数器和程序状态字的内容的同时产生用于启动宏服务处理的宏服务请求。 数据存储器用于启动宏服务处理的控制信息和用于执行多个宏服务处理的命令信息。 控制信息包括与宏服务处理对应的命令信息的基地址。 中断控制器响应来自中断请求产生装置的宏服务处理请求，并将单个宏服务请求信号输出到中央处理单元，并直接访问允许中央处理单元连续工作的数据存储器。

公开(公告)号：US4847867A

公开(公告)日：1989-07-11

申请号：US91803

申请日：1987-09-01

申请人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

发明人： Masaki Nasu ,  Shigetatsu Katori ,  Yukio Maehashi ,  Kazutoshi Yoshizawa

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4077 ,  G06F13/4256

摘要： A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

摘要翻译： 公开了一种串行数据通信系统。 该系统包括通过单个时钟线和单个数据线互连的多个站。 站中的主站包括用于驱动时钟线的晶体管推挽电路，以在时钟线上输出时钟信号。 因此，时钟信号具有尖锐的引导和下降沿。 数据线耦合到线逻辑装置。 发送站与时钟信号的相关联的时钟脉冲的前沿和下降沿中的一个同步地在数据线上传输数据信号的每一位，并且接收站与另一个的同步接收数据信号的每一位 相关时钟脉冲的前沿和下降沿。

公开(公告)号：US5163150A

公开(公告)日：1992-11-10

申请号：US691297

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。 虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

公开(公告)号：US5036458A

公开(公告)日：1991-07-30

申请号：US287622

申请日：1988-12-20

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。 处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。 在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。

公开(公告)号：US4949242A

公开(公告)日：1990-08-14

申请号：US268330

申请日：1988-11-04

申请人： Kazuhiro Takeuchi ,  Shigetatsu Katori

发明人： Kazuhiro Takeuchi ,  Shigetatsu Katori

IPC分类号： G06F13/28 ,  G11C8/04

CPC分类号： G11C8/04

摘要： A microcomputer comprises a microprocessor chip and a memory chip coupled to each other. The memory chip includes a memory for storing various processing data, a bus interface for designating an address information of the memory to be accessed for a data transfer, and an address latch for temporarily holding the address information from the bus interface and so as to supply the address information to the memory. Furthermore, there is provided an automatically updated data pointer whose initial value is set with the address information supplied from the bus interface. In case of individually designating an address for each item of data to be transferred, the address latch is used to supply the address information to the memory so that an address is given to the address latch by the bus interface for each data transfer of one unitary data. In the case of continuously designating an address for each item of data to be transferred, so that the data pointer is used to supply the address information to the memory so that an address for the data transfer of a first unitary data to be transferred is given to the data pointer and then the data pointer is automatically updated for each of the second and succeeding data transfers.

公开(公告)号：US4839797A

公开(公告)日：1989-06-13

申请号：US759006

申请日：1985-07-25

申请人： Shigetatsu Katori ,  Yukio Maehashi

发明人： Shigetatsu Katori ,  Yukio Maehashi

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/455

CPC分类号： G06F9/30174 ,  G06F9/30189

摘要： A microprocessor includes a central processing unit which executes a program according to at least one control signal generated by an instruction decoder. The instruction decoder is designed such that a first type instruction compatible for the central processing unit can be decoded. A second type instruction not compatible for the central processing unit is applied as an address to a conversion memory in which a first type instruction corresponding in function to the second type instruction has been stored. The first type instruction in the conversion memory is then applied to the instruction decoder instead of the second type instruction. Thus, the second type instruction can be executed by the central processing unit which is not otherwise compatible with the second type instruction.

摘要翻译： 微处理器包括中央处理单元，该中央处理单元根据由指令解码器产生的至少一个控制信号来执行程序。 指令解码器被设计成使得能够解码与中央处理单元兼容的第一类型指令。 将不兼容中央处理单元的第二类型指令作为地址应用于其中已经存储了与第二类型指令功能相对应的第一类型指令的转换存储器。 然后转换存储器中的第一类型指令被施加到指令解码器而不是第二类型指令。 因此，第二类型的指令可以由与第二类型指令不兼容的中央处理单元执行。