公开(公告)号：US5159688A

公开(公告)日：1992-10-27

申请号：US691284

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

公开(公告)号：US5163150A

公开(公告)日：1992-11-10

申请号：US691297

申请日：1991-04-25

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行和中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新启动由中断到堆栈存储器的程序执行所必需的信息的堆栈操作。 虽然处理器可以在没有堆栈操作的情况下响应于第二模式信号执行中断操作，从而可以提供具有较少开销的改进的处理器。

公开(公告)号：US5036458A

公开(公告)日：1991-07-30

申请号：US287622

申请日：1988-12-20

申请人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

发明人： Osamu Matsushima ,  Yukio Maehashi ,  Shigetatsu Katori ,  Masahiro Nomura ,  Hiroko Shinohara ,  Kohichi Kariya ,  Mitsue Abe

IPC分类号： G06F13/32

CPC分类号： G06F13/32

摘要： An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

摘要翻译： 信息处理器具有至少一个接口单元，通过该接口单元将处理器耦合到外围设备。 当处理器根据来自外围设备的请求执行中断操作时，接口单元可以选择性地产生第一模式信号或第二模式信号。 当处理器响应于第一模式信号执行中断操作时，在中断操作开始之前执行用于保存重新执行由堆栈存储器中的中断而停止的程序所需的信息的堆栈操作。 处理器可以在不进行堆栈操作的情况下响应于第二模式信号执行中断操作，从而提供具有较少开销的改进的处理器。 在多种应用中描述了两种中断模式技术，包括D / A转换，串行数据传输和接收以及计算机外围设备的操作。

公开(公告)号：US4964141A

公开(公告)日：1990-10-16

申请号：US182006

申请日：1988-04-15

申请人： Osamu Matsushima ,  Yukio Maehashi

发明人： Osamu Matsushima ,  Yukio Maehashi

IPC分类号： G06F13/38 ,  G06F13/00 ,  H04L1/16 ,  H04L5/16 ,  H04L7/00 ,  H04L7/04 ,  H04L29/08

CPC分类号： H04L7/0008 ,  H04L5/16 ,  H04L1/1692

摘要： A serial data processor is coupled to a single data line and a single clock line for serial data transfer in synchronism with a clock signal. The data processor comprises a shift register coupled to the serial data line and operated to serially output the data in synchronism with a clock on the clock line, and an output buffer connected to receive the data serially outputted from the shift register and coupled to sequentially output the received data to the data line. This output buffer includes a push-pull driver having an output connected to the data line and an input driven by the data serially outputted from the shift register. A clock counter is coupled to receive the clock on the clock line so as to maintain the push-pull driver in an operable condition until the count value reaches a predetermined value and to bring the output of the push-pull driver into a floating condition after the count value reached a predetermined value. There is provided a data line control circuit coupled to the data line and controlled by the clock counter to bring the data line to a high level after the count value of the clock counter reaches the predetermined value.

公开(公告)号：US5410715A

公开(公告)日：1995-04-25

申请号：US8387

申请日：1993-01-25

申请人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

发明人： Satomi Ishimoto ,  Osamu Matsushima ,  Masaki Nasu ,  Masahiro Nomura

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： An interrupt controller comprises a circuit for holding information obtained by designating one priority selected from a plurality of priorities for each of a plurality of interrupt requests, and a flag for indicating whether or not a nesting is allowed for an interrupt request having at least one predetermined priority of the plurality of priorities. On the basis of the priority information held in the circuit and information held in the flag, a controller operates so that when an interrupt request is generated in the course of execution of an interrupt processing having the predetermined priority, if the flag is in a first condition, the controller acknowledges the generated interrupt request only when the priority of the generated interrupt request is higher than the predetermined priority, and if the flag is in a second condition, the controller acknowledges the generated interrupt request not only when the priority of the generated interrupt request is higher than the predetermined priority, but also when the priority of the generated interrupt request is the same as the predetermined priority.

摘要翻译： 中断控制器包括一个电路，用于保存通过指定从多个中断请求中的每一个的多个优先级中选择的一个优先级获得的信息，以及用于指示是否允许具有至少一个预定的中断请求的中断请求的嵌套的标志 优先考虑多项优先事项。 基于保持在电路中的优先级信息和保持在标志中的信息，控制器操作，使得当在执行具有预定优先级的中断处理的过程中产生中断请求时，如果该标志位于第一 条件是，只有当所产生的中断请求的优先级高于预定优先级时，控制器才确认产生的中断请求，并且如果标志处于第二状态，则控制器不仅在生成的中断请求的优先级 中断请求高于预定优先级，而且当所产生的中断请求的优先级与预定优先级相同时。

公开(公告)号：US20110024859A1

公开(公告)日：2011-02-03

申请号：US12937013

申请日：2009-03-30

申请人： Kenichi Miyazaki ,  Osamu Matsushima ,  Shigeru Niki ,  Keiichiro Sakurai ,  Shogo Ishizuka

发明人： Kenichi Miyazaki ,  Osamu Matsushima ,  Shigeru Niki ,  Keiichiro Sakurai ,  Shogo Ishizuka

IPC分类号： H01L31/0232 ,  H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14645 ,  H01L31/0322

摘要： A photoelectric conversion device has a high S/N ratio and can increase the detection efficiency even under a low luminance. The photoelectric conversion device generates an increased electric charge by impact ionization in a photoelectric conversion unit formed from a chalcopyrite type semiconductor, so as to improve dark current characteristic. The photoelectric conversion device includes: a lower electrode layer; a compound semiconductor thin film of chalcopyrite structure disposed on the lower electrode layer and having a high resistivity layer on a surface; and a transparent electrode layer disposed on the compound semiconductor thin film, wherein the lower electrode layer, the compound semiconductor thin film, and the transparent electrode layer are laminated one after another, and a reverse bias voltage is applied between the transparent electrode layer and the lower electrode layer, and the multiplication by the impact ionization of the electric charge generated by photoelectric conversion is generated within the compound semiconductor thin film. It is also possible to provide a fabrication method for such photoelectric conversion device, and a solid state imaging device using the photoelectric conversion device.

摘要翻译： 光电转换装置的S / N比高，即使在低亮度下也能够提高检测效率。 光电转换装置通过由黄铜矿型半导体形成的光电转换单元中的冲击电离产生增加的电荷，从而改善暗电流特性。 光电转换装置包括：下电极层; 黄铜矿结构的化合物半导体薄膜设置在下电极层上并且在表面上具有高电阻率层; 以及设置在化合物半导体薄膜上的透明电极层，其中下电极层，化合物半导体薄膜和透明电极层依次层叠，并且在透明电极层和透明电极层之间施加反向偏置电压 并且在化合物半导体薄膜内产生通过光电转换产生的电荷的冲击电离的乘积。 也可以提供这种光电转换装置的制造方法和使用该光电转换装置的固态成像装置。

公开(公告)号：US20100295145A1

公开(公告)日：2010-11-25

申请号：US12781850

申请日：2010-05-18

申请人： Kenichi Miyazaki ,  Osamu Matsushima

发明人： Kenichi Miyazaki ,  Osamu Matsushima

IPC分类号： H01L31/105 ,  H01L31/18 ,  H01L31/0264

CPC分类号： H01L31/0322 ,  H01L31/0336 ,  H01L31/105 ,  H01L31/109 ,  Y02E10/541

摘要： A light-absorbing layer is composed of a compound-semiconductor film of charcopyrite structure, a surface layer is disposed on the light-absorbing layer, the surface layer having a higher band gap energy than the compound-semiconductor film, an upper electrode layer is disposed on the surface layer, and a lower electrode layer is disposed on a backside of the light-absorbing layer in opposition to the upper electrode layer, the upper electrode layer and the lower electrode layer having a reverse bias voltage applied in between to detect electric charges produced by photoelectric conversion in the compound-semiconductor film, as electric charges due to photoelectric conversion are multiplied by impact ionization, while the multiplication by impact ionization of electric charges is induced by application of a high-intensity electric field to a semiconductor of charcopyrite structure, allowing for an improved dark-current property, and an enhanced efficiency even in detection of low illumination intensities, with an enhanced S/N ratio.

摘要翻译： 光吸收层由正铁矿结构的化合物半导体膜构成，表面层设置在光吸收层上，表面层具有比化合物半导体膜更高的带隙能量，上电极层为 配置在表面层上，下电极层设置在与上电极层相对的光吸收层的背面，上电极层和下电极层之间施加反向偏压，以检测电 在化合物半导体膜中通过光电转换产生的电荷由于光电转换而产生的电荷乘以冲击电离，而电荷的冲击电离的乘积是通过向高锰酸盐半导体施加高强度电场而引起的 结构，允许改善的暗电流特性，以及即使在低光的检测中也提高了效率 内生强度，S / N比提高。

公开(公告)号：US06402011B1

公开(公告)日：2002-06-11

申请号：US09633293

申请日：2000-08-04

申请人： Masahiro Taniguchi ,  Kazumi Ishimoto ,  Koichi Nagai ,  Osamu Yamazaki ,  Tatsuaki Kitagawa ,  Osamu Matsushima ,  Kazuhiro Uji ,  Seizo Nemoto

发明人： Masahiro Taniguchi ,  Kazumi Ishimoto ,  Koichi Nagai ,  Osamu Yamazaki ,  Tatsuaki Kitagawa ,  Osamu Matsushima ,  Kazuhiro Uji ,  Seizo Nemoto

IPC分类号： B23K3102

CPC分类号： B23K3/085 ,  B23K1/008 ,  B23K2101/42 ,  H05K3/3415 ,  H05K3/3447 ,  H05K3/3494 ,  H05K2203/087 ,  H05K2203/304

摘要： For reflow soldering, radiant heating is applied to one surface of a printed circuit board on which electronic components are placed and onto which cream solder is supplied and at the same time hot air is blown locally and roughly perpendicular to to-be-connected points on said one surface of the printed circuit board. This reflow method permits secure soldering even if the hot air is set at a temperature not exceeding the heat resistance of the electronic components, which is possilbe because of its combination with the radiant heat. Moreover, this reflow method can permit soldering in such a manner that only the to-be-connected points are heated selectively, because the hot air is blown locally and roughly perpendicular to the points to be connected. Thus, this reflow method prevents heat damage to other sections than the to-be-connected points and ensures that the solder at the to-be-connected points is melted.

摘要翻译： 对于回流焊接，辐射加热被施加到印刷电路板的放置电子部件的一个表面上，并且在其上供应奶油焊膏，并且同时热空气局部地被吹送并大致垂直于待连接点 所述印刷电路板的一个表面。 这种回流方法即使热空气被设定在不超过电子部件的耐热性的温度下，由于与辐射热的组合，所以能够进行安全的焊接。 此外，这种回流方法可以以这样的方式允许焊接，即只有待连接点被选择性地加热，因为热空气局部地吹动并且大致垂直于要连接的点。 因此，这种回流方法可防止对待连接点的其他部分的热损伤，并确保待连接点处的焊料熔化。

公开(公告)号：US5649219A

公开(公告)日：1997-07-15

申请号：US708884

申请日：1996-09-04

申请人： Osamu Matsushima

发明人： Osamu Matsushima

IPC分类号： G06F15/78 ,  G06F11/26 ,  G06F11/273 ,  G06F11/00

CPC分类号： G06F11/261 ,  G06F11/2733

摘要： In a microcomputer with built-in SOG region system debugging is made possible using a gate array provided outside the microcomputer by supplying signals transferred between a CPU and the gate array to external terminals used for transferring signals between the interior of the microcomputer and a peripheral device outside the microcomputer. In order to supply necessary signals to the gate array connected to the external terminals, a selection circuit which outputs signals between CPU and the SOG region to the external terminals by means of a mode switching signal is provided. By the provision of the selection circuit, it becomes possible to output the signals between the CPU and the SOG region to the external terminals by switching, and to transmit the signals of CPU to the gate array provided outside the microcomputer. Accordingly, it becomes possible to debug the system using the gate array provided outside the microcomputer.

摘要翻译： 在具有内置SOG区域的微型计算机中，通过将在CPU和门阵列之间传送的信号提供给外部终端，用于在微计算机的内部和外围设备之间传送信号，使用在微计算机外部提供的门阵列可以进行调试 在微机外 为了向连接到外部端子的门阵列提供必要的信号，提供了通过模式切换信号将CPU和SOG区域之间的信号输出到外部端子的选择电路。 通过提供选择电路，可以通过切换将CPU和SOG区域之间的信号输出到外部端子，并将CPU的信号发送到设置在微型计算机外部的门阵列。 因此，可以使用设置在微计算机外部的门阵列来调试系统。

公开(公告)号：US5208781A

公开(公告)日：1993-05-04

申请号：US704157

申请日：1991-05-22

申请人： Osamu Matsushima

发明人： Osamu Matsushima

IPC分类号： G11C11/41 ,  G06F1/32 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F1/3215 ,  G06F1/3275 ,  Y02B60/1225 ,  Y02B60/1228

摘要： A memory device includes a memory, an address latch, a built-in incrementer, and an address decoder. The address decoder has a mapping register which assigns the memory to a predetermined address. The address decoder further includes a standby signal producer which detects whether or not the address latch addresses an address specified by the mapping register and which sets the memory device to a standby state of a low power consumption when such is not detected. The memory device can be set to a standby state even when the memory device is connected to a microcomputer with a protocol by which an address of the memory is not outputted each time. This arrangement enables to save power consumption of the computer, to decrease the load of a power supply circuit in a microcomputer applied apparatus and to make the apparatus compact.