公开(公告)号：US08106437B2

公开(公告)日：2012-01-31

申请号：US11311165

申请日：2005-12-20

申请人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

发明人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

IPC分类号： H01L27/108

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).

摘要翻译： 提供半导体存储装置，其抑制电池之间的短路以提高操作可靠性并且有助于高速操作。 由形成在硅衬底（1）中的隔离沟槽（40）限定形成DRAM单元的有源区（7）。 隔离沟槽（40）在其中形成隔离绝缘膜（4）。 每个DRAM单元包括具有侧壁（13）的栅极（12）和具有侧壁（23）的上电极（22）的电容器的MOS晶体管。 在隔离沟槽（40）的上部形成有凹部（41），电容器的上部电极（22）埋设在凹部（41）中。 上电极（22）的埋入部的外缘（E1）位于侧壁（23）的外缘（E2）的内侧。

公开(公告)号：US20060138512A1

公开(公告)日：2006-06-29

申请号：US11311165

申请日：2005-12-20

申请人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

发明人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).

摘要翻译： 提供半导体存储装置，其抑制电池之间的短路以提高操作可靠性并且有助于高速操作。 由形成在硅衬底（1）中的隔离沟槽（40）限定形成DRAM单元的有源区（7）。 隔离沟槽（40）在其中形成隔离绝缘膜（4）。 每个DRAM单元包括具有侧壁（13）的栅极（12）和具有侧壁（23）的上电极（22）的电容器的MOS晶体管。 在隔离沟槽（40）的上部形成有凹部（41），电容器的上部电极（22）埋设在凹部（41）中。 上部电极（22）的埋入部分的外边缘（E 1 SUB）位于侧壁（23）的外边缘（E 2 2 N）内。