公开(公告)号：US08106437B2

公开(公告)日：2012-01-31

申请号：US11311165

申请日：2005-12-20

申请人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

发明人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

IPC分类号： H01L27/108

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).

摘要翻译： 提供半导体存储装置，其抑制电池之间的短路以提高操作可靠性并且有助于高速操作。 由形成在硅衬底（1）中的隔离沟槽（40）限定形成DRAM单元的有源区（7）。 隔离沟槽（40）在其中形成隔离绝缘膜（4）。 每个DRAM单元包括具有侧壁（13）的栅极（12）和具有侧壁（23）的上电极（22）的电容器的MOS晶体管。 在隔离沟槽（40）的上部形成有凹部（41），电容器的上部电极（22）埋设在凹部（41）中。 上电极（22）的埋入部的外缘（E1）位于侧壁（23）的外缘（E2）的内侧。

公开(公告)号：US20060138512A1

公开(公告)日：2006-06-29

申请号：US11311165

申请日：2005-12-20

申请人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

发明人： Hidenori Sato ,  Hiroyasu Nousou ,  Yoshitaka Fujiishi ,  Hiroaki Sekikawa

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/1087

摘要： A semiconductor storage device is provided, which inhibits shorts between cells to improve operational reliability and contributes to high-speed operation. An active region (7) where DRAM cells are formed is defined by an isolation trench (40) formed in a silicon substrate (1). The isolation trench (40) has an isolation insulating film (4) formed therein. Each DRAM cell includes a MOS transistor having a gate electrode (12) with sidewalls (13), and a capacitor having an upper electrode (22) with sidewalls (23). A recess (41) is formed in the upper portion of the isolation trench (40), and the upper electrode (22) of the capacitor has a buried portion buried in the recess (41). The outer edge (E1) of the buried portion of the upper electrode (22) is located inside the outer edge (E2) of the sidewalls (23).

摘要翻译： 提供半导体存储装置，其抑制电池之间的短路以提高操作可靠性并且有助于高速操作。 由形成在硅衬底（1）中的隔离沟槽（40）限定形成DRAM单元的有源区（7）。 隔离沟槽（40）在其中形成隔离绝缘膜（4）。 每个DRAM单元包括具有侧壁（13）的栅极（12）和具有侧壁（23）的上电极（22）的电容器的MOS晶体管。 在隔离沟槽（40）的上部形成有凹部（41），电容器的上部电极（22）埋设在凹部（41）中。 上部电极（22）的埋入部分的外边缘（E 1 SUB）位于侧壁（23）的外边缘（E 2 2 N）内。

公开(公告)号：US06743693B2

公开(公告)日：2004-06-01

申请号：US10301698

申请日：2002-11-22

申请人： Yoshitaka Fujiishi

发明人： Yoshitaka Fujiishi

IPC分类号： H01L2120

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91

摘要： A photomask includes patterns corresponding to openings, a pattern corresponding to a trench and dummy patterns not to be transferred to a photoresist. The patterns are arranged in a matrix at a second pitch in the column direction and at a first pitch in the row direction. The dummy patterns are spaced at the second pitch from the most adjacent ones of the patterns aligned in the row direction, and the dummy patterns are spaced at a first pitch from the most adjacent ones of the patterns aligned in the column direction. Using such photomask, openings on each of which a lower electrode of a capacitor is to be formed are formed in an insulation layer in a memory cell array forming region, and the trench is formed in the insulation layer at the border between the memory cell array forming region and a peripheral circuit forming region.

摘要翻译： 光掩模包括对应于开口的图案，对应于沟槽的图案和不被转印到光致抗蚀剂的伪图案。 图案以列方向上的第二间距以行方向的第一间距排列成矩阵。 虚拟图案以与行方向对齐的最靠近的图案的第二间距间隔开，并且虚设图案以与在列方向上排列的最相邻的图案中的最靠近的图案间隔开。 使用这样的光掩模，在存储单元阵列形成区域的绝缘层中形成要形成电容器的下部电极的开口，并且沟槽形成在存储单元阵列之间的边界处的绝缘层中 形成区域和外围电路形成区域。

公开(公告)号：US20060246676A1

公开(公告)日：2006-11-02

申请号：US11411921

申请日：2006-04-27

申请人： Yoshitaka Fujiishi

发明人： Yoshitaka Fujiishi

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower electrode of capacitors of DRAM cells extends into the inner walls of the isolation trench exposed by the opening, and a dielectric layer is formed in almost constant thickness on the inner walls and bottom of the isolation trench exposed by the opening. An upper electrode is partially buried in the opening. A channel cut layer is formed in the vicinity of the bottom of the opening.

摘要翻译： 在硅衬底的上部的隔离沟槽中形成隔离绝缘膜。 隔离绝缘膜具有开口，通过该开口露出隔离沟槽的内壁和底部。 用作DRAM单元的电容器的下电极的下扩散层延伸到由开口暴露的隔离沟槽的内壁中，并且电介质层以绝对厚度形成在隔离槽的内壁和底部， 开幕。 上电极部分地埋在开口中。 在开口底部附近形成通道切割层。

公开(公告)号：US06828636B2

公开(公告)日：2004-12-07

申请号：US10134426

申请日：2002-04-30

申请人： Yoshitaka Fujiishi ,  Satoshi Kawasaki

发明人： Yoshitaka Fujiishi ,  Satoshi Kawasaki

IPC分类号： H01L2704

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L27/0629

摘要： Excessive CMP (chemical mechanical polishing) of a resistive band region and margin deterioration in processing in a subsequent step are prevented, while a resistive zone is formed with an active region. In the semiconductor device, a source/drain impurity diffusion layer is used as the resistive zone. On a semiconductor substrate, the resistive band region to form the resistive zone, having at least a portion of a surface provided as the active region, is formed. In the resistive band region, the resistive zone is provided. A word line is arranged on the semiconductor substrate so as to surround the resistive zone. In the resistive band region, the area occupancy ratio of the active region per 10 &mgr;m□ is set to be 40% or higher.

摘要翻译： 防止电阻带区域的CMP（化学机械抛光）和随后的步骤中的处理中的边缘劣化，同时形成有效区域的电阻区域。 在半导体器件中，使用源/漏杂质扩散层作为电阻区。 在半导体衬底上形成形成电阻带的电阻带区，其具有至少一部分作为有源区的表面。 在电阻带区域中，提供电阻区域。 在半导体衬底上布置字线以包围电阻区。 在电阻带区域中，每10um□的有源区域的面积占有率设定为40％以上。

公开(公告)号：US06703287B2

公开(公告)日：2004-03-09

申请号：US09791763

申请日：2001-02-26

申请人： Yoshitaka Fujiishi ,  Atsushi Ueno

发明人： Yoshitaka Fujiishi ,  Atsushi Ueno

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/31053

摘要： An improved method for producing a semiconductor device in which overpolishing is prevented at a chemical mechanical polishing time to eliminate the influence of peripheries on the object part. A plasma oxide film is formed on a semiconductor substrate so as to fill a recess and a trench. With the use of a resist film as a mask, the plasma oxide film is selectively etched to leave an overpolish-preventing support member in a neighborhood of the recess, which is a photo-related mark, for providing a support against overpolishing at a chemical mechanical polishing time. The surface of the semiconductor substrate is polished by chemical mechanical polishing. Thereafter, a nitride film and an oxide film are removed.

摘要翻译： 一种用于制造半导体器件的改进方法，其中在化学机械抛光时间期间防止了过度抛光以消除外围对物体部分的影响。 在半导体基板上形成等离子体氧化膜，以填充凹槽和沟槽。 通过使用抗蚀剂膜作为掩模，选择性地蚀刻等离子体氧化物膜以在作为光相关标记的凹部附近留下防多余的支撑构件，以提供用于在化学品上过度抛光的支撑 机械抛光时间。 通过化学机械抛光对半导体基板的表面进行抛光。 之后，除去氮化物膜和氧化物膜。

公开(公告)号：US06455381B1

公开(公告)日：2002-09-24

申请号：US09440700

申请日：1999-11-16

申请人： Masahiro Shimizu ,  Yoshitaka Fujiishi

发明人： Masahiro Shimizu ,  Yoshitaka Fujiishi

IPC分类号： H01L21336

CPC分类号： H01L21/823481 ,  H01L21/76224

摘要： A method of manufacturing a semiconductor devices includes the formation of a pad insulating film, a polysilicon film and a silicon nitride film on a semiconductor substrate. A trench portion is formed in the substrate after etching, and silicon oxide is embedded in the trench portion. The silicon nitride film, polysilicon film, and pad insulating film are then removed to expose a surface of the semiconductor substrate. The removal of the polysilicon film is by isotropic wet etching. A circuit element is formed on the exposed surfaces of the semiconductor substrate.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成衬垫绝缘膜，多晶硅膜和氮化硅膜。 在蚀刻之后，在衬底中形成沟槽部分，并且氧化硅嵌入在沟槽部分中。 然后去除氮化硅膜，多晶硅膜和焊盘绝缘膜以暴露半导体衬底的表面。 通过各向同性的湿蚀刻去除多晶硅膜。 电路元件形成在半导体衬底的暴露表面上。

公开(公告)号：US07348235B2

公开(公告)日：2008-03-25

申请号：US11411921

申请日：2006-04-27

申请人： Yoshitaka Fujiishi

发明人： Yoshitaka Fujiishi

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： An isolation insulation film is formed in an isolation trench in an upper portion of a silicon substrate. The isolation insulation film has an opening by which inner walls and bottom of the isolation trench are exposed. A lower diffusion layer serving as a lower electrode of capacitors of DRAM cells extends into the inner walls of the isolation trench exposed by the opening, and a dielectric layer is formed in almost constant thickness on the inner walls and bottom of the isolation trench exposed by the opening. An upper electrode is partially buried in the opening. A channel cut layer is formed in the vicinity of the bottom of the opening.

摘要翻译： 在硅衬底的上部的隔离沟槽中形成隔离绝缘膜。 隔离绝缘膜具有开口，通过该开口露出隔离沟槽的内壁和底部。 用作DRAM单元的电容器的下电极的下扩散层延伸到由开口暴露的隔离沟槽的内壁中，并且电介质层以绝对厚度形成在隔离槽的内壁和底部， 开幕。 上电极部分地埋在开口中。 在开口底部附近形成通道切割层。

公开(公告)号：US06596582B2

公开(公告)日：2003-07-22

申请号：US10271580

申请日：2002-10-17

申请人： Yoshitaka Fujiishi ,  Yoshinori Tanaka ,  Eiji Hasunuma

发明人： Yoshitaka Fujiishi ,  Yoshinori Tanaka ,  Eiji Hasunuma

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/84 ,  H01L28/91

摘要： There can be provided a semiconductor device having a rough surface to provide an increased capacitance of a capacitor and enhanced prevention of short-circuit between capacitors, and a method of manufacturing the same. The semiconductor device includes a plug interconnection penetrating an insulating film and connected to an underlying wiring, and a storage node having a lower portion overlying the insulating film and free of a rough surface, and connected to the plug interconnection, and an upper portion overlying the lower portion of the storage node without covering a side surface of the lower portion of the storage node, and having a rough surface.

摘要翻译： 可以提供具有粗糙表面以提供电容器的增加的电容并增强电容器之间短路的防止的半导体器件及其制造方法。 半导体器件包括穿透绝缘膜并连接到下面的布线的插头互连，以及具有覆盖绝缘膜并且没有粗糙表面的下部并且连接到插头互连的下部的存储节点，以及覆盖 存储节点的下部，而不覆盖存储节点的下部的侧表面，并且具有粗糙表面。