公开(公告)号：US07971043B2

公开(公告)日：2011-06-28

申请号：US11944416

申请日：2007-11-22

Applicant: Li-Hung Chang ,  Hong-Men Su

Inventor： Li-Hung Chang ,  Hong-Men Su

IPC: G06F9/38 ,  G06F15/76

CPC classification number: G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3869 ,  G06F9/3873

Abstract: An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.

Abstract translation: 电子系统包括具有串联耦合的第一数量的流水线级的流水线，流水线控制单元和逻辑引擎，其中流水线中的每个流水线级用于在时钟信号的每个周期将数据输出到下一流水线级 。 流水线控制单元用于将流水线中的第一数量的流水线级改变为第二数量的流水线级。 该逻辑引擎用于利用具有第一数量的流水线级的流水线以第一模式执行电子系统的操作，并且通过利用具有第二数量的流水线级的管线，以第二模式执行电子系统的操作。 耦合到管道和逻辑引擎的频率控制单元和电压控制单元分别相应地调整电子系统的频率和电压。

公开(公告)号：US20100124308A1

公开(公告)日：2010-05-20

申请号：US12271924

申请日：2008-11-16

Applicant: Chuan-Hua Chang ,  Hong-Men Su

Inventor： Chuan-Hua Chang ,  Hong-Men Su

IPC: H03K21/00

CPC classification number: H03K21/38 ,  G06F9/30018

Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.

Abstract translation: 为了在比特流提取期间有效地处理边界条件，当设置下溢标志时，从比特流寄存器的最高有效位开始从比特流寄存器提取预定数量的比特。 预定数量等于预定的提取宽度减去先前的开始位置。 这些位被存储在目标寄存器的最低部分，并且下溢标志被清除。

公开(公告)号：US07822999B2

公开(公告)日：2010-10-26

申请号：US11757411

申请日：2007-06-04

Applicant: Li-Hung Chang ,  Hong-Men Su ,  Chuan-Hua Chang

Inventor： Li-Hung Chang ,  Hong-Men Su ,  Chuan-Hua Chang

IPC: G06F1/00 ,  G06F1/26 ,  G11C5/14 ,  H04B1/38

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.

Abstract translation: 提供了一种用于控制其处理器的计算机系统和方法。 处理器管理单元（PMU）由处理器本身或由另一处理器根据处理器的工作状态的变化来编程。 然后，当处理器进入待机模式时，处理器将通知信号发送到PMU。 PMU接收到通知信号后，根据变更调整处理器的运行状况。 最后，在处理器的工作状态改变稳定之后，PMU向处理器发送一个完成信号。 因此，可以避免在调整操作条件期间由处理器过早唤醒引起的不可预知的行为。

公开(公告)号：US20060149947A1

公开(公告)日：2006-07-06

申请号：US11002393

申请日：2004-12-01

Applicant: Hong-Men Su

Inventor： Hong-Men Su

IPC: G06F9/00

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3812

Abstract: A method of predicting branch instructions and a method of skipping branch instructions for pipelines which need more than one cycle to predict branch direction and branch target addresses in microprocessors and digital signal processors are provided. The address of an instruction executed before the predicted branch is used as an index to enable early branch prediction so that the address of the instruction predicted to be executed immediately after the branch is available earlier, thereby reducing the number of idle or wasted clock cycles.

Abstract translation: 提供了一种预测分支指令的方法和跳过用于需要多于一个周期以预测微处理器和数字信号处理器中的分支方向和分支目标地址的管线的分支指令的方法。 在预测分支之前执行的指令的地址用作能够进行早期分支预测的索引，使得预先在分支之后预先执行的指令的地址更早地获得，从而减少空闲或浪费的时钟周期的数量。

公开(公告)号：US08171188B2

公开(公告)日：2012-05-01

申请号：US12271924

申请日：2008-11-16

Applicant: Chuan-Hua Chang ,  Hong-Men Su

Inventor： Chuan-Hua Chang ,  Hong-Men Su

IPC: G06F5/14 ,  G06F7/24

CPC classification number: H03K21/38 ,  G06F9/30018

Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.

Abstract translation: 为了在比特流提取期间有效地处理边界条件，当设置下溢标志时，从比特流寄存器的最高有效位开始从比特流寄存器提取预定数量的比特。 预定数量等于预定的提取宽度减去先前的开始位置。 这些位被存储在目标寄存器的最低部分，并且下溢标志被清除。

公开(公告)号：US20090138674A1

公开(公告)日：2009-05-28

申请号：US11944416

申请日：2007-11-22

Applicant: Li-Hung Chang ,  Hong-Men Su

Inventor： Li-Hung Chang ,  Hong-Men Su

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3869 ,  G06F9/3873

Abstract: An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.

Abstract translation: 电子系统包括具有串联耦合的第一数量的流水线级的流水线，流水线控制单元和逻辑引擎，其中流水线中的每个流水线级用于在时钟信号的每个周期将数据输出到下一流水线级 。 流水线控制单元用于将流水线中的第一数量的流水线级改变为第二数量的流水线级。 该逻辑引擎用于利用具有第一数量的流水线级的流水线以第一模式执行电子系统的操作，并且通过利用具有第二数量的流水线级的管线，以第二模式执行电子系统的操作。 耦合到管道和逻辑引擎的频率控制单元和电压控制单元分别相应地调整电子系统的频率和电压。

公开(公告)号：US20080140986A1

公开(公告)日：2008-06-12

申请号：US11608247

申请日：2006-12-08

Applicant: Chuan-Hua Chang ,  Hong-Men Su ,  Jen-Chih Tseng

Inventor： Chuan-Hua Chang ,  Hong-Men Su ,  Jen-Chih Tseng

IPC: G06F12/06

CPC classification number: G06F9/30145 ,  G06F9/30134 ,  G06F9/384

Abstract: A method is disclosed for accessing a target register of a plurality of registers. The method includes: receiving an instruction containing a register index field; and mapping the register index field to the target register access index for accessing the target register. A data accessing apparatus corresponding to this method is also disclosed.

Abstract translation: 公开了一种用于访问多个寄存器的目标寄存器的方法。 该方法包括：接收包含寄存器索引字段的指令; 并将寄存器索引字段映射到用于访问目标寄存器的目标寄存器访问索引。 还公开了与该方法对应的数据访问装置。

公开(公告)号：US06920510B2

公开(公告)日：2005-07-19

申请号：US10163047

申请日：2002-06-05

Applicant: Gary Chang ,  Hong-men Su

Inventor： Gary Chang ,  Hong-men Su

IPC: G06T9/00 ,  G06F3/00 ,  G06F3/06 ,  G06F5/00

CPC classification number: G06T9/007

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract translation: 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于一个或多个控制信号经由单个端口存储器在多个第一端口和第二端口之间传送数据。 第二电路可以被配置为产生一个或多个控制信号，其中存储器在第二端口和多个第一端口之间是时间共享的。

公开(公告)号：US08756605B2

公开(公告)日：2014-06-17

申请号：US11015055

申请日：2004-12-17

Applicant: Kathirgamar Aingaran ,  Hong-Men Su

Inventor： Kathirgamar Aingaran ,  Hong-Men Su

IPC: G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/3842 ,  G06F9/4881 ,  G06F2209/483

Abstract: An apparatus and method for scheduling execution of multiple threads on a shared processor resource is described in connection with a multithreaded multiprocessor chip. Using a thread selection policy that switches between available threads every cycle to give priority to the least recently executed or scheduled threads, different threads are able to operate in a way that ensures no deadlocks or livelocks while maximizing aggregate performance and fairness between threads. Prioritization is accomplished by monitoring and sorting thread status information for each thread, including speculative states in which a thread may be speculatively scheduled, thereby improving usage of the execution pipeline by switching a thread in with a lower priority.

Abstract translation: 结合多线程多处理器芯片描述了用于调度共享处理器资源上的多个线程的执行的装置和方法。 使用线程选择策略，每个周期在可用线程之间切换，以优先考虑最近执行或调度的最短线程，不同的线程能够以确保没有死锁或活锁的方式进行操作，同时最大限度地提高线程之间的总体性能和公平性。 通过监视和排序每个线程的线程状态信息来确定优先级，包括可以推测性调度线程的推测状态，从而通过以较低优先级切换线程来改善执行流水线的使用。

公开(公告)号：US07934073B2

公开(公告)日：2011-04-26

申请号：US11685773

申请日：2007-03-14

Applicant: Chuan-Hua Chang ,  Hong-Men Su

Inventor： Chuan-Hua Chang ,  Hong-Men Su

IPC: G06F12/00

CPC classification number: G06F9/322 ,  G06F9/30181 ,  G06F9/4812 ,  G06F12/10

Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.

Abstract translation: 公开了一种用于同时执行跳转和转换状态改变过程的方法。 该方法包括：以第一翻译状态在第一功能中执行一系列指令处理; 并执行在第二功能中跳转到目标地址的跳转指令，并同时启动并完成翻译状态改变为第二翻译状态; 其中在所述跳转指令之后的下一条指令的地址作为返回地址被存储在第一寄存器中。