公开(公告)号：US07934037B2

公开(公告)日：2011-04-26

申请号：US12847965

申请日：2010-07-30

申请人： Horng-Yee Chou ,  Szu-Kuang Chou ,  Kuang-Yu Wang ,  I-Kang Yu

发明人： Horng-Yee Chou ,  Szu-Kuang Chou ,  Kuang-Yu Wang ,  I-Kang Yu

IPC分类号： G06F3/00 ,  G06F13/12 ,  H05K7/10

CPC分类号： G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  H01R13/26 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods for communicating using various protocols through the Secured Digital (SD) physical interface are disclosed. The invention covers, among others, single-mode and multi-mode hosts, single-mode and multi-mode devices, as well as techniques for initializing these hosts and devices in order to facilitate the aforementioned communication.

摘要翻译： 公开了使用各种协议通过安全数字（SD）物理接口进行通信的系统和方法。 本发明尤其涉及单模和多模式主机，单模和多模式装置，以及用于初始化这些主机和装置以便于上述通信的技术。

公开(公告)号：US07457897B1

公开(公告)日：2008-11-25

申请号：US10803597

申请日：2004-03-17

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-Pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-Pieng Peter Kao

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US20080065794A1

公开(公告)日：2008-03-13

申请号：US11928124

申请日：2007-10-30

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An extended Universal-Serial Bus (EUSB) host has reduced loading by using radio frequency (RF) transceivers or direct wiring traces rather than a pair of legacy USB cables. The reduced loading opens the eye pattern. The EUSB device transfers internal data using chained Direct-Memory Access (DMA). Registers in a DMA controller point to a vector table that has vector entries, each pointing to a destination and a source. The source is a memory table for a memory group. The memory table has entries for several memory segments. Each memory-table entry has a pointer to a memory segment and a byte count for the segment. Once all bytes in the segment are transferred, a flag in the entry indicates when another memory segment follows within the memory group. When an END flag is read, then vector table is advanced to the next vector entry, and another memory group of memory segments processed.

摘要翻译： 扩展的通用串行总线（EUSB）主机通过使用射频（RF）收发器或直接布线轨迹而不是一对传统的USB电缆减少了负载。 减少负荷打开眼睛图案。 EUSB设备使用链接的直接内存访问（DMA）传输内部数据。 DMA控制器中的寄存器指向具有向量条目的向量表，每个向量表指向一个目的地和一个源。 源是内存组的内存表。 内存表有几个内存段的条目。 每个存储表条目具有指向存储器段的指针和段的字节计数。 一旦片段中的所有字节都被传送，该条目中的标志表示在存储器组中跟随其他内存段的时间。 读取END标志时，向量表前进到下一个向量条目，并处理另一个内存段的内存组。

公开(公告)号：US20080046608A1

公开(公告)日：2008-02-21

申请号：US11925933

申请日：2007-10-27

申请人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles Lee ,  David Chow ,  Abraham Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F3/00

CPC分类号： G06F13/4045 ,  Y02D10/14 ,  Y02D10/151

摘要： An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an EUSB device that is busy performing a memory or other operation. Power is saved since polling is avoided. The busy EUSB device sends a not-yet NYET signal back to the EUSB host to instruct the host to enter the suspend mode. When the EUSB device is ready to continue transfer with the host, the EUSB device wakes up the host by sending a ready RDY signal back to the host. The NYET and RDY signals may be tokens or flags in serial packets sent over a full-duplex connection to the host with two sets of differential pairs. Transfers may be re-started by the host after suspension once the requested data is read from flash memory, or space is made available in a sector buffer by completing earlier writes to flash memory.

摘要翻译： 扩展的通用串行总线（EUSB）主机进入暂停模式，而不是轮询正忙于执行内存或其他操作的EUSB设备。 省电，因为避免轮询。 繁忙的EUSB设备向EUSB主机发送一个尚未发送的NYET信号，指示主机进入挂起模式。 当EUSB设备准备好继续与主机进行传输时，EUSB设备通过将准备好的RDY信号发送回主机来唤醒主机。 NYET和RDY信号可以是通过全双工连接发送到具有两组差分对的主机的串行数据包中的令牌或标志。 一旦所请求的数据从闪存中读取，主机可以重新启动传输，或者通过完成对闪存的更早写入，在扇区缓冲器中可用空间。

公开(公告)号：US07186147B1

公开(公告)日：2007-03-06

申请号：US10939051

申请日：2004-09-10

申请人： Horng-Yee Chou ,  Ren-Kang Chiou ,  Edward W. Lee

发明人： Horng-Yee Chou ,  Ren-Kang Chiou ,  Edward W. Lee

IPC分类号： H01R24/00

CPC分类号： G06K19/07732 ,  G06K19/07733 ,  H01R24/62 ,  H01R27/02

摘要： A peripheral device having a device processor, a multi-personality bus switch, and an extended Universal-Serial Bus (USB) plug is disclosed. The peripheral device is capable of communicating with a host computer using one or more protocols. The extended Universal-Serial Bus (USB) plug includes an extended pin substrate, the extended pin substrate and at least some of a plurality of contacts thereon being dimensioned to be mechanically compatible with an industry-standard USB socket. The extended USB plug further lacks an industry-standard cover associated with an industry-standard USB plug, thereby causing the extended USB plug to be thinner than the industry-standard USB plug.

摘要翻译： 公开了一种具有设备处理器，多人性总线开关和扩展的通用串行总线（USB）插头的外围设备。 外围设备能够使用一个或多个协议与主机通信。 扩展的通用串行总线（USB）插头包括扩展的引脚基板，延伸的引脚基板和其上的多个触点中的至少一些触点的尺寸被设计成与工业标准USB插座机械兼容。 扩展的USB插头还缺少与行业标准USB插头相关的行业标准封面，从而使扩展的USB插头比行业标准的USB插头更薄。

公开(公告)号：US20060294272A1

公开(公告)日：2006-12-28

申请号：US11467134

申请日：2006-08-24

申请人： Horng-Yee Chou ,  Ren-Kang Chiou ,  Szu-Kuang Chou

发明人： Horng-Yee Chou ,  Ren-Kang Chiou ,  Szu-Kuang Chou

IPC分类号： G06F13/38

CPC分类号： G06K19/07732 ,  G06K19/07733 ,  H01R24/62 ,  H01R27/02

摘要： Host computers and peripheral devices communicating through extended USB connectors and plugs are disclosed. The host computer and peripheral device are capable of communicating via multiple communication modes, using the extended capability of the extended USB connectors and plugs. Software and hardware to facilitate such communication are also disclosed.

摘要翻译： 公开了通过扩展USB连接器和插头进行通信的主机和外围设备。 使用扩展USB连接器和插头的扩展功能，主机和外围设备能够通过多种通信模式进行通信。 还公开了促进这种通信的软件和硬件。

公开(公告)号：US07126873B2

公开(公告)日：2006-10-24

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles C. Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles C. Lee

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02 ,  G06F12/06

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories.In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US07125287B1

公开(公告)日：2006-10-24

申请号：US10834457

申请日：2004-04-28

申请人： Horng-Yee Chou ,  Ren-Kang Chiou ,  Szu-Kuang Chou

发明人： Horng-Yee Chou ,  Ren-Kang Chiou ,  Szu-Kuang Chou

IPC分类号： H01R24/00

CPC分类号： H01R13/26 ,  G06K19/07732 ,  G06K19/07733 ,  H01R12/725 ,  H01R13/658

摘要： Extended Universal-Serial-Bus (USB) plugs and sockets are disclosed. The extended USB plug includes an extended pin substrate having an extended substrate length longer than a length of a pin substrate of an industry-standard USB connector plug. There is further included a plurality of USB connector contacts configured to carry USB signals and a plurality of non-USB connector contacts configured to carry non-USB signals. The extended Universal-Serial-Bus (USB) plug, which includes an extended pin substrate having an extended substrate length longer than a length of a pin substrate of an industry-standard USB connector plug. There is included a plurality of USB connector contacts configured to carry USB signals and a plurality of non-USB connector contacts configured to carry non-USB signals.

摘要翻译： 公开了扩展的通用串行总线（USB）插头和插座。 扩展的USB插头包括延伸的衬底长度比工业标准USB连接器插头的引脚衬底的长度更长的扩展引脚衬底。 还包括配置成承载USB信号的多个USB连接器触点和被配置为携带非USB信号的多个非USB连接器触点。 扩展的通用串行总线（USB）插头，其包括延伸的引脚基板，其延伸的基板长度比工业标准USB连接器插头的引脚基板的长度长。 包括被配置为承载USB信号的多个USB连接器触点和被配置为携带非USB信号的多个非USB连接器触点。

公开(公告)号：US07103684B2

公开(公告)日：2006-09-05

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US07073010B2

公开(公告)日：2006-07-04

申请号：US10707276

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F13/20

CPC分类号： G06F13/385

摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.

摘要翻译： 双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。 当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。 相邻的事务可以通过重新排序重叠。 在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。 数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。