公开(公告)号：US20050120157A1

公开(公告)日：2005-06-02

申请号：US10707276

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F13/20 ,  G06F13/38

CPC分类号： G06F13/385

摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.

摘要翻译： 双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。 当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。 相邻的事务可以通过重新排序重叠。 在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。 数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。

公开(公告)号：US20050138288A1

公开(公告)日：2005-06-23

申请号：US10746935

申请日：2003-12-23

申请人： Horng-Yee Chou ,  Ben Wei Chen ,  Sun-Teck See

发明人： Horng-Yee Chou ,  Ben Wei Chen ,  Sun-Teck See

IPC分类号： G06F12/00 ,  G06F13/40

CPC分类号： G06F13/409

摘要： A flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a first serial interface coupled to the ExpressCard™ connector, and a controller coupled to the first serial interface and the at least one flash memory module.

摘要翻译： 用于连接到ExpressCard TM主机的闪存设备包括至少一个闪存模块，用于连接到ExpressCard TM主机的ExpressCard TM连接器，耦合到ExpressCard TM连接器的第一串行接口， 以及耦合到所述第一串行接口和所述至少一个闪存模块的控制器。

公开(公告)号：US20050120146A1

公开(公告)日：2005-06-02

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US07103684B2

公开(公告)日：2006-09-05

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles C. Lee

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US07073010B2

公开(公告)日：2006-07-04

申请号：US10707276

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F13/20

CPC分类号： G06F13/385

摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.

摘要翻译： 双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。 当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。 相邻的事务可以通过重新排序重叠。 在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。 数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。

公开(公告)号：US20050160218A1

公开(公告)日：2005-07-21

申请号：US10761853

申请日：2004-01-20

申请人： Sun-Teck See ,  Tzu-Yih Chu ,  Ben-Wei Chen ,  Horng-yee Chou ,  Szu-Kuang Chou ,  Charles Lee

发明人： Sun-Teck See ,  Tzu-Yih Chu ,  Ben-Wei Chen ,  Horng-yee Chou ,  Szu-Kuang Chou ,  Charles Lee

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F13/405 ,  G06F3/0601 ,  G06F13/1694 ,  G06F2003/0694

摘要： A FLASH controller is disclosed. The controller comprises a USB interface unit. The USB interface unit implements a USB standard that has a bus speed equal or greater than 12 Mb/s. The controller includes an internal bus coupled to the USB interface unit; and a FLASH interface unit coupled to the internal bus. The FLASH interface unit includes FLASH controller logic that allows the throughput for access to the FLASH memory to match the speed of the USB standard. Advantages of the FLASH controller in accordance with the present invention include (1) utilizing the higher speed USB interface such as the USB 2.0 standard, which substantially increases the serial throughput between USB host and FLASH controller; (2) utilizing more advanced FLASH control logic which is implemented to raise the throughput for the FLASH memory access; (3) utilizing an intelligent algorithm to detect and access the different FLASH types, which broadens the sourcing and the supply of FLASH memory; (4) by storing the software program along with data in FLASH memory which results in the cost of the controller being reduced, and also makes the software program field changeable and upgradeable; and (5) providing high integration, which substantially reduces the overall space needed and reduces the complexity and the cost of manufacturing.

摘要翻译： 公开了一种闪存控制器。 控制器包括USB接口单元。 USB接口单元实现总线速度等于或大于12 Mb / s的USB标准。 该控制器包括耦合到USB接口单元的内部总线; 以及耦合到内部总线的FLASH接口单元。 FLASH接口单元包括FLASH控制器逻辑，允许访问闪速存储器的吞吐量与USB标准的速度相匹配。 根据本发明的闪存控制器的优点包括（1）利用诸如USB 2.0标准的更高速USB接口，其大大增加了USB主机和闪存控制器之间的串行吞吐量; （2）利用更高级的FLASH控制逻辑，其实现以提高FLASH存储器访问的吞吐量; （3）利用智能算法检测和访问不同的FLASH类型，拓宽了FLASH存储器的采购和供应; （4）通过将软件程序与FLASH存储器中的数据一起存储，从而降低控制器的成本，并使软件程序区域可以更改和升级; 和（5）提供高集成度，这大大降低了所需的总体空间并降低了制造的复杂性和成本。

公开(公告)号：US20050114587A1

公开(公告)日：2005-05-26

申请号：US10707138

申请日：2003-11-22

申请人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G06F12/00 ,  G06F13/38

CPC分类号： G06F13/385

摘要： An ExpressCard contains flash memory. The ExpressCard has an ExpressCard connector that plugs into a host, such as a personal computer, digital camera, or personal digital assistant (PDA). A controller chip on the ExpressCard uses a pair of differential Universal-Serial-Bus (USB) data lines in the connector to communicate with the USB host, or can use PCI Express, Firewire, or other protocols. One or more flash-memory chips on the ExpressCard are controlled by a flash-memory controller in the controller chip. Two or more channels of a flash bus have a shared control bus but separate ready lines. The separate ready lines allow flash-memory chips in the two channels to finish operations at different times.

摘要翻译： ExpressCard包含闪存。 ExpressCard具有插入主机的ExpressCard连接器，如个人计算机，数码相机或个人数字助理（PDA）。 ExpressCard上的控制器芯片使用连接器中的一对差分通用串行总线（USB）数据线与USB主机进行通信，也可以使用PCI Express，Firewire或其他协议。 ExpressCard上的一个或多个闪存芯片由控制器芯片中的闪存控制器控制。 闪存总线的两个或更多个通道具有共享控制总线，但是分离的就绪线路。 单独的就绪线路允许两个通道中的闪存芯片在不同时间完成操作。

公开(公告)号：US20090049222A1

公开(公告)日：2009-02-19

申请号：US12254428

申请日：2008-10-20

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-pieng Peter Kao

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US07457897B1

公开(公告)日：2008-11-25

申请号：US10803597

申请日：2004-03-17

申请人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-Pieng Peter Kao

发明人： Charles C. Lee ,  Sun-Teck See ,  Horng-Yee Chou ,  I-Pieng Peter Kao

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

摘要翻译： 兼容PCI Express的闪存设备可以包括一个或多个闪存模块，控制器和ExpressCard接口。 控制器可以有利地提供PCI Express功能以及闪速存储器操作，例如， 使用ExpressCard接口进行写入，读取或擦除。 PIO接口包括向闪存设备发送第一和第二存储器请求包。 第一存储器请求分组包括为所需操作准备闪存设备的命令字设置。 如果需要，第二存储器请求分组触发操作并且包括数据有效载荷。 DMA接口包括将第二存储器请求从闪存设备发送到主机，从而触发主机释放用于DMA操作的系统总线。

公开(公告)号：US07126873B2

公开(公告)日：2006-10-24

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles C. Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles C. Lee

IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C16/04 ,  G06F12/02 ,  G06F12/06

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories.In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。