公开(公告)号：US5132926A

公开(公告)日：1992-07-21

申请号：US586415

申请日：1990-09-21

申请人： Stuart P. MacEachern ,  Alan C. Marshall ,  Howard C. Salwen

发明人： Stuart P. MacEachern ,  Alan C. Marshall ,  Howard C. Salwen

IPC分类号： H04L7/027 ,  H04L12/433 ,  H04L25/03

CPC分类号： H04L25/03019 ,  H04L12/433

摘要： An improved local area network ring node of the type described in ANSI/IEEE Standard 802.5, including a receiver having an input connectable to the ring, a phase-locked loop circuit for extracting a clock frequency from the receiver output and including a phase detector for generating a phase error signal, and a data demodulator connected for demodulating at the extracted clock frequency the data in the receiver output. The improvement lies in the provision of a filter for deriving a control signal from the outputs of the data demodulator and the phase detector and an adaptive equalizer for reducing the effect of jitter in signals applied to the receiver input from the network, the equalizer comprising a filter network including a voltage variable impedance so connected as to vary responsively to the control signal.

摘要翻译： ANSI / IEEE标准802.5中描述类型的改进的局域网环形节点，包括具有可连接到环的输入的接收器，用于从接收器输出提取时钟频率的锁相环电路，并且包括用于 产生相位误差信号，以及数据解调器，连接用于在提取的时钟频率上对接收机输出中的数据进行解调。 改进之处在于提供一种用于从数据解调器和相位检测器的输出端导出控制信号的滤波器和用于减少施加到来自网络的接收机输入的信号中的抖动影响的自适应均衡器，该均衡器包括 滤波器网络包括如此连接的电压可变阻抗，以响应于控制信号变化。

公开(公告)号：US5090025A

公开(公告)日：1992-02-18

申请号：US558197

申请日：1990-07-24

申请人： Alan C. Marshall ,  Stuart P. MacEachern ,  Howard C. Salwen

发明人： Alan C. Marshall ,  Stuart P. MacEachern ,  Howard C. Salwen

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L12/42 ,  H04L25/60 ,  H04L27/227

CPC分类号： H04L27/2272 ,  H04L12/422 ,  H04L7/033

摘要： An improved local area network node of the type described in ANSI/IEEE Standard 802.5, including a receiver-demodulator having an input connectable to the ring and having a received data output and a received clock output, an elasticity buffer connected to the received data output, a modulator for modulating the output of the buffer in accordance with a signal at a clocking input of the modulator, and a phase-locked loop interposed between the received clock output of the demodulator and the clocking input of the modulator, the loop including a voltage-controlled oscillator, a phase detector and a filter connected for providing a control-voltage to the oscillator.

摘要翻译： ANSI / IEEE标准802.5中所述类型的改进的局域网节点，包括接收机解调器，其具有可连接到环的输入端并具有接收的数据输出和接收到的时钟输出;连接到接收的数据输出的弹性缓冲器 调制器，用于根据调制器的时钟输入处的信号调制缓冲器的输出，以及插入在解调器的接收时钟输出端和调制器的时钟输入端之间的锁相环，该环路包括一个 压控振荡器，相位检测器和连接用于向振荡器提供控制电压的滤波器。