公开(公告)号：US20060076548A1

公开(公告)日：2006-04-13

申请号：US11246863

申请日：2005-10-07

申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

IPC分类号： H01L29/02

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

公开(公告)号：US07479405B2

公开(公告)日：2009-01-20

申请号：US11982940

申请日：2007-11-06

申请人： Jae-hyun Park ,  Hyeong-geun An ,  Su-jin Ahn ,  Yoon-jong Song ,  Hyung-joo Youn ,  Kyu-chul Kim

发明人： Jae-hyun Park ,  Hyeong-geun An ,  Su-jin Ahn ,  Yoon-jong Song ,  Hyung-joo Youn ,  Kyu-chul Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

公开(公告)号：US20080070344A1

公开(公告)日：2008-03-20

申请号：US11982940

申请日：2007-11-06

申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

IPC分类号： H01L45/00

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

公开(公告)号：US20080014511A1

公开(公告)日：2008-01-17

申请号：US11777863

申请日：2007-07-13

申请人： Do-Yul YOO ,  Ji-Yong YOU ,  Joong-Sung KIM ,  Hyung-Joo YOUN

发明人： Do-Yul YOO ,  Ji-Yong YOU ,  Joong-Sung KIM ,  Hyung-Joo YOUN

IPC分类号： G03C5/00 ,  G03F9/00 ,  G03F1/00

CPC分类号： G03F7/70633

摘要： Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

摘要翻译： 提供了一种光掩模和一种制造半导体器件的方法。 光掩模包括具有芯片区域和划线路区域的光掩模基板，在划线路区域形成有覆盖标记。 覆盖标记包括一个或多个子覆盖标记。 每个子覆盖标记包括彼此顺序连接并且具有不同宽度的多个单位区域，其中给定单位区域的宽度是恒定的。

公开(公告)号：US07732105B2

公开(公告)日：2010-06-08

申请号：US11777863

申请日：2007-07-13

申请人： Do-Yul Yoo ,  Ji-Yong You ,  Joong-Sung Kim ,  Hyung-Joo Youn

发明人： Do-Yul Yoo ,  Ji-Yong You ,  Joong-Sung Kim ,  Hyung-Joo Youn

IPC分类号： G03F1/00 ,  G03F9/00

CPC分类号： G03F7/70633

摘要： Provided are a photomask and a method of fabricating a semiconductor device. The photomask includes a photomask substrate including a chip region and a scribe lane region, with an overlay mark formed in the scribe lane region. The overlay mark includes one or more sub-overlay marks. Each of the sub-overlay marks includes a plurality of unit regions sequentially connected to each other and having different widths, where the width of a given unit region is constant.

摘要翻译： 提供了一种光掩模和一种制造半导体器件的方法。 光掩模包括具有芯片区域和划线路区域的光掩模基板，在划线路区域形成有覆盖标记。 覆盖标记包括一个或多个子覆盖标记。 每个子覆盖标记包括彼此顺序连接并且具有不同宽度的多个单位区域，其中给定单位区域的宽度是恒定的。

公开(公告)号：US07309885B2

公开(公告)日：2007-12-18

申请号：US11246863

申请日：2005-10-07

申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

IPC分类号： H01L27/10

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。