公开(公告)号：US07348277B2

公开(公告)日：2008-03-25

申请号：US11352640

申请日：2006-02-13

申请人： Ja-Eung Koo ,  Byung-Lyul Park

发明人： Ja-Eung Koo ,  Byung-Lyul Park

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/7688 ,  H01L21/76819

摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

摘要翻译： 提供了使用牺牲层制造半导体器件的方法。 这些方法提供了一种在大理石工艺中进行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。 为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。 在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。 在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。 依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。 在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

公开(公告)号：US20060183333A1

公开(公告)日：2006-08-17

申请号：US11352640

申请日：2006-02-13

申请人： Ja-Eung Koo ,  Byung-Lyul Park

发明人： Ja-Eung Koo ,  Byung-Lyul Park

IPC分类号： H01L21/461 ,  C23F1/00 ,  B44C1/22

CPC分类号： H01L21/7688 ,  H01L21/76819

摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

摘要翻译： 提供了使用牺牲层制造半导体器件的方法。 这些方法提供了一种在大理石过程中执行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。 为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。 在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。 在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。 依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。 在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

公开(公告)号：US06976902B2

公开(公告)日：2005-12-20

申请号：US10850688

申请日：2004-05-21

申请人： Ja-Eung Koo ,  Jong-Won Lee ,  Sung-Bae Lee ,  Duk-Ho Hong ,  Sang-Rok Hah ,  Hong-Seong Son

发明人： Ja-Eung Koo ,  Jong-Won Lee ,  Sung-Bae Lee ,  Duk-Ho Hong ,  Sang-Rok Hah ,  Hong-Seong Son

IPC分类号： B24B37/02 ,  B24B37/04 ,  B24B49/10 ,  B24B49/14 ,  B24B1/00

CPC分类号： B24B37/013 ,  B24B49/10 ,  B24B49/14

摘要： There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.

摘要翻译： 提供了一种化学机械抛光装置，其可以包括由抛光台马达旋转并且具有垫的抛光台，位于抛光台上方的载体头可以通过载体头马达的驱动旋转并具有晶片 位于其底部的浆料供应器，用于向抛光台的上部供应浆料;第一抛光终点检测器，用于通过温度传感器的温度变化检测抛光终点;至少一个检测温度传感器 抛光区域（晶片，焊盘和浆料）的温度，以及用于从承载头电动机的负载电流，电压和电阻的变化检测抛光终点的第二抛光终点检测器。 此外，代替第二研磨终点检测器，可以采用光信号抛光终点检测器，用于通过照射在晶片上的光并从晶片反射来检测抛光终点。

公开(公告)号：US07595253B2

公开(公告)日：2009-09-29

申请号：US11797827

申请日：2007-05-08

申请人： II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

发明人： II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

摘要翻译： 示例性实施例提供半导体器件及其形成方法。 根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。 封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。 结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

公开(公告)号：US20080081406A1

公开(公告)日：2008-04-03

申请号：US11750491

申请日：2007-05-18

申请人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

发明人： Jae-ouk Choo ,  II-young Yoon ,  Seo-woo Nam ,  Ja-eung Koo

IPC分类号： H01L29/739

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.

摘要翻译： 一种制造半导体器件的方法，包括在PMOS区上提供包括PMOS区和PMOS栅电极的NMOS区和在NMOS栅区上的NMOS栅电极的衬底，所述衬底在形成的PMOS区上形成应力衬垫 PMOS晶体管上的PMOS栅极和NMOS区域上形成有NMOS栅电极的NMOS区域，并以惰性蒸气气氛，选择性地将辐射施加到形成在PMOS区域和NMOS区域中的任一个上的应力衬垫上。

公开(公告)号：US20070262393A1

公开(公告)日：2007-11-15

申请号：US11797827

申请日：2007-05-08

申请人： Il-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

发明人： Il-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

IPC分类号： H01L29/76 ,  H01L21/76 ,  H01L21/461 ,  H01L29/94 ,  H01L21/302 ,  H01L31/00

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

摘要翻译： 示例性实施例提供半导体器件及其形成方法。 根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。 封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。 结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

公开(公告)号：US20060151887A1

公开(公告)日：2006-07-13

申请号：US11326301

申请日：2006-01-05

申请人： Jun-Hwan Oh ,  Ja-Eung Koo ,  Se-Jong Park

发明人： Jun-Hwan Oh ,  Ja-Eung Koo ,  Se-Jong Park

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure and a method of fabricating the same are provided. The interconnection structure includes an interlayer insulating layer having a structure comprising a via hole structure or a trench-shaped line structure. A conformal metal diffusion barrier layer is disposed inside the via hole structure or the trench-shaped line structure of the interlayer insulating layer. An insulating diffusion barrier spacer is disposed to cover the metal diffusion barrier layer on the sidewalls of the via hole structure or the trench-shaped line structure of the interlayer insulating layer. In addition, a copper interconnection is disposed to fill the inside of the via hole structure or the trench-shaped line structure of the interlayer insulating layer.

摘要翻译： 提供互连结构及其制造方法。 互连结构包括具有包括通孔结构或沟槽状线结构的结构的层间绝缘层。 保形金属扩散阻挡层设置在层间绝缘层的通孔结构或沟槽状线结构的内部。 设置绝缘扩散阻挡间隔物以覆盖通孔结构的侧壁上的金属扩散阻挡层或层间绝缘层的沟槽状线结构。 此外，布置铜互连以填充层间绝缘层的通孔结构或沟槽状线结构的内部。

公开(公告)号：US06924207B2

公开(公告)日：2005-08-02

申请号：US10696438

申请日：2003-10-29

申请人： Hong-Seong Son ,  Sang-Rok Hah ,  Ja-Eung Koo

发明人： Hong-Seong Son ,  Sang-Rok Hah ,  Ja-Eung Koo

IPC分类号： H01L23/52 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L27/0805

摘要： A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在ssubstrate上形成互连线。 互连线用作第一电极。 在包括金属互连线的基板上形成第一绝缘层。 在第一绝缘层上形成电极层和氧化物层。 在氧化物层上形成光刻胶图形。 使用光致抗蚀剂图案作为蚀刻掩模蚀刻氧化物层和电极层。 结果，在互连线上形成堆叠的第二电极和氧化物层图案。 至少使用湿蚀刻技术蚀刻电极层。 然后去除光致抗蚀剂图案。

公开(公告)号：US20080132030A1

公开(公告)日：2008-06-05

申请号：US11950306

申请日：2007-12-04

申请人： Il-Young YOON ,  Dong-Suk SHIN ,  Jae-Ouk CHOO ,  Ja-Eung KOO

发明人： Il-Young YOON ,  Dong-Suk SHIN ,  Jae-Ouk CHOO ,  Ja-Eung KOO

IPC分类号： H01L21/762

CPC分类号： H01L21/31053 ,  H01L21/76224

摘要： After sequentially forming an insulating layer and a capping dielectric layer having a higher density than the insulating layer, a chemical mechanical polishing (CMP) process is performed to prevent scratch from being formed on the surface of the insulating layer at the early stage of the CMP process. Thus, a semiconductor device with improved reliability is achieved.

摘要翻译： 在顺序地形成具有比绝缘层更高的密度的绝缘层和封盖电介质层之后，进行化学机械抛光（CMP）工艺以防止在CMP的早期在绝缘层的表面上形成划痕 处理。 因此，实现了可靠性提高的半导体器件。

公开(公告)号：US20080045018A1

公开(公告)日：2008-02-21

申请号：US11826899

申请日：2007-07-19

申请人： Il-young Yoon ,  Jae-ouk Choo ,  Ja-eung Koo

发明人： Il-young Yoon ,  Jae-ouk Choo ,  Ja-eung Koo

IPC分类号： H01L21/461

CPC分类号： H01L21/31053 ,  C09G1/02

摘要： A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the insulating layer, wherein the first slurry includes a first abrasive and ionic surfactants having a zeta potential with a second polarity opposite to the first polarity. The method of forming an isolation layer includes forming a mask layer on a substrate, etching the substrate to a desired depth using the mask layer such that a trench is formed in the substrate, forming the insulating layer on the substrate and performing the first chemical-mechanical polishing operation described above.

摘要翻译： 提供化学机械抛光（CMP）的方法和使用其形成隔离层的方法。 化学机械抛光方法包括通过在绝缘层上提供第一浆料，对具有第一极性的ζ电位的绝缘层进行第一化学机械抛光操作，其中第一浆料包括第一磨料和离子表面活性剂，其具有 具有与第一极性相反的第二极性的ζ电位。 形成隔离层的方法包括在衬底上形成掩模层，使用掩模层将衬底蚀刻到所需的深度，使得在衬底中形成沟槽，在衬底上形成绝缘层，并执行第一化学 - 上述机械抛光操作。