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    Implementing fixed-point polynomials in hardware logic
    2.
    发明授权
    Implementing fixed-point polynomials in hardware logic 有权

    公开(公告)号：US11809795B2

    公开(公告)日：2023-11-07

    申请号：US17323373

    申请日：2021-05-18

    Applicant: Imagination Technologies Limited

    Inventor： Theo Alan Drane

    IPC: G06F30/327

    CPC classification number: G06F30/327

    Abstract: A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached.

    ERROR BOUNDED MULTIPLICATION BY INVARIANT RATIONALS
    3.
    发明申请
    ERROR BOUNDED MULTIPLICATION BY INVARIANT RATIONALS 有权

    公开(公告)号：US20210165634A1

    公开(公告)日：2021-06-03

    申请号：US17171174

    申请日：2021-02-09

    Applicant: Imagination Technologies Limited

    Inventor： Theo Alan Drane

    IPC: G06F7/523 ,  G06F7/38 ,  G06F7/535 ,  G06F30/327

    Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.

    Partially and fully parallel normaliser
    4.
    发明授权
    Partially and fully parallel normaliser 有权

    公开(公告)号：US10223068B2

    公开(公告)日：2019-03-05

    申请号：US15636100

    申请日：2017-06-28

    Applicant: Imagination Technologies Limited

    Inventor： Theo Alan Drane

    IPC: G06F5/01 ,  G06F7/74

    Abstract: Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.

    Method and apparatus for use in the design and manufacture of integrated circuits
    5.
    发明授权
    Method and apparatus for use in the design and manufacture of integrated circuits 有权

    公开(公告)号：US10162600B2

    公开(公告)日：2018-12-25

    申请号：US15898455

    申请日：2018-02-17

    Applicant: Imagination Technologies Limited

    Inventor： Theo Alan Drane ,  Wai-Chuen Cheung

    IPC: G06F7/38 ,  G06F7/535 ,  G06F17/50

    Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

    Trailing or Leading Digit Anticipator
    6.
    发明申请
    Trailing or Leading Digit Anticipator 审中-公开
    追踪或领先的数字预测者

    公开(公告)号：US20170075658A1

    公开(公告)日：2017-03-16

    申请号：US15262168

    申请日：2016-09-12

    Applicant: Imagination Technologies Limited

    Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

    IPC: G06F7/74

    CPC classification number: G06F7/74

    Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

    Abstract translation: 方法和领先的零预测器，用于估计固定点算术运算结果中的前导零数，这对任何带符号的固定点数都精确到一位以内。 前置零预测器包括输入编码电路，其从固定点数生成编码输入串; 基于窗口的代理串生成电路，其生成代数串，其前导码是通过检查编码输入串的连续窗口并设置代理串的相应位的算术运算结果中的前导码的估计值， 考试; 以及计数器电路，被配置为基于所述替代串中的前一个来估计所述算术运算结果中的前导零的数目。

    Trailing or Leading Zero Counter Having Parallel and Combinational Logic
    7.
    发明申请
    Trailing or Leading Zero Counter Having Parallel and Combinational Logic 审中-公开

    公开(公告)号：US20160335055A1

    公开(公告)日：2016-11-17

    申请号：US15218306

    申请日：2016-07-25

    Applicant: Imagination Technologies Limited

    Inventor： Freddie Rupert Exall ,  Theo Alan Drane

    IPC: G06F7/74 ,  G06F9/30

    CPC classification number: G06F7/74 ,  G06F9/30029

    Abstract: A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

    Trailing or leading zero counter having parallel and combinational logic
    8.
    发明授权
    Trailing or leading zero counter having parallel and combinational logic 有权
    具有并行和组合逻辑的跟踪或前导零计数器

    公开(公告)号：US09424030B2

    公开(公告)日：2016-08-23

    申请号：US14598459

    申请日：2015-01-16

    Applicant: Imagination Technologies Limited

    Inventor： Freddie Rupert Exall ,  Theo Alan Drane

    IPC: G06F7/00 ,  G06F9/30 ,  G06F7/74

    CPC classification number: G06F7/74 ,  G06F9/30029

    Abstract: A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

    Abstract translation: 尾部/前导零计数器包括多个硬件逻辑块，每个硬件逻辑块计算输出值的一个位（即，尾随/前导零的数量，取决于它是否是尾部/前导零计数器）。 每个硬件逻辑块包括两个部分硬件逻辑块，每个块部分接收输入串的一部分并从该部分的位产生一个或两个输出。 组合逻辑然后组合部分硬件逻辑的输出以生成输出值的位。 对于计算除输出的最低有效位之外的位的硬件逻辑块，硬件逻辑块还包括一个或多个OR还原级，通过使用OR门的比特组合来减少输入串的长度，所得到的字符串是 分为两部分，并输入到硬件逻辑部分。

    Method and apparatus for synthesising a sum of addends operation and an integrated circuit
    9.
    发明授权
    Method and apparatus for synthesising a sum of addends operation and an integrated circuit 有权
    用于合成加法运算和集成电路之和的方法和装置

    公开(公告)号：US08943447B2

    公开(公告)日：2015-01-27

    申请号：US13921471

    申请日：2013-06-19

    Applicant: Imagination Technologies Limited

    Inventor： Theo Alan Drane ,  Thomas Rose

    IPC: G06F9/45 ,  G06F17/50 ,  G06F9/455 ,  G06F7/523 ,  G06F7/499 ,  G06F7/509 ,  G06F7/533

    CPC classification number: G06F7/523 ,  G06F7/49947 ,  G06F7/509 ,  G06F7/5338 ,  G06F17/5045

    Abstract: A method is provided for a synthesizing In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimization constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (20). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived (22) and those columns are discarded (24). Next, a number of bits which can be removed from the least significant column is derived (26) and these bits are discarded (28). The constant is included in the sum of addends and a logic array synthesized in RTL (31) before manufacturing an integrated circuit.

    Abstract translation: 提供了一种用于合成In RTL，逻辑电路和用于制造用于执行具有忠实舍入的加法和的集成电路的方法。 在此，确定可以被丢弃的比特值的优化约束和包括在加数之和中的常数的优化约束（20）。 接下来，导出可以从加数数组的总和中删除的整个列的最大数目（22），并丢弃那些列（24）。 接下来，导出可以从最低有效列移除的位数（26），并丢弃这些位（28）。 在制造集成电路之前，常数包括在加数和RTL（31）中合成的逻辑阵列之和。

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