公开(公告)号：US08598944B2

公开(公告)日：2013-12-03

申请号：US13556364

申请日：2012-07-24

申请人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

发明人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

IPC分类号： G11C5/14

CPC分类号： G06F1/3296 ,  H03K19/0008 ,  Y02D10/172

摘要： According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

摘要翻译： 根据一个实施例，半导体集成电路包括半导体集成电路，提供规定电源电压的电压调节器，多个延迟测试电路，每个延迟测试电路被配置在响应于电流流动的每个区域中 对于每种运行模式，测试控制单元在逐步降低电源电压的同时在测试模式下使用延迟测试电路执行延迟测试，电源电压判定单元决定操作模式的电源电压 在延迟测试的基础上，存储单元存储每个操作模式的电源电压，电源电压配置单元从存储器单元读出与操作模式相对应的电源电压，以及供应配置单元布置 当每个操作模式开始执行时，电源电压作为电压调节器的输出电压。

公开(公告)号：US20130207692A1

公开(公告)日：2013-08-15

申请号：US13556364

申请日：2012-07-24

申请人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

发明人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

IPC分类号： H03K5/153

CPC分类号： G06F1/3296 ,  H03K19/0008 ,  Y02D10/172

摘要： According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

摘要翻译： 根据一个实施例，半导体集成电路包括半导体集成电路，提供规定电源电压的电压调节器，多个延迟测试电路，每个延迟测试电路被配置在响应于电流流动的每个区域中 对于每种运行模式，测试控制单元在逐步降低电源电压的同时在测试模式下使用延迟测试电路执行延迟测试，电源电压判定单元决定操作模式的电源电压 在延迟测试的基础上，存储单元存储每个操作模式的电源电压，电源电压配置单元从存储器单元读出与操作模式相对应的电源电压，以及供应配置单元布置 当每个操作模式开始执行时，电源电压作为电压调节器的输出电压。

公开(公告)号：US20110032262A1

公开(公告)日：2011-02-10

申请号：US12716782

申请日：2010-03-03

申请人： Toshiyuki Furusawa ,  Hitoshi Nemoto ,  Isao Ooigawa ,  Nariyuki Fukuda ,  Hiroyuki Fujioka ,  Noriyuki Moriyasu

发明人： Toshiyuki Furusawa ,  Hitoshi Nemoto ,  Isao Ooigawa ,  Nariyuki Fukuda ,  Hiroyuki Fujioka ,  Noriyuki Moriyasu

IPC分类号： G09G5/36

CPC分类号： G09G5/395 ,  G06T1/60 ,  G09G5/36 ,  G09G5/393 ,  G09G2340/0492 ,  G09G2360/18

摘要： A normal bus and an extension bus having the same bit width as the normal bus are provided. A line buffer has a plurality of line regions to store pixel data of input image data. A line buffer writing control portion controls a direction in which the pixel data is to be written to the line buffer. A line buffer reading control portion reads out the pixel data stored in the line buffer and to output the read out pixel data to the buses selectively. A frame memory writing control portion controls a destination in a frame memory to which the pixel data obtained from the buses is to be written. An address control portion controls a writing address in the frame memory. The line buffer writing control portion controls the writing direction in the line buffer in accordance with an image rotation command signal.

摘要翻译： 提供具有与正常总线相同的位宽度的普通总线和扩展总线。 行缓冲器具有多个行区域以存储输入图像数据的像素数据。 行缓冲器写入控制部分控制将像素数据写入行缓冲器的方向。 行缓冲器读取控制部分读出存储在行缓冲器中的像素数据并选择性地将读出的像素数据输出到总线。 帧存储器写入控制部分控制要从总线获得的像素数据被写入的帧存储器中的目的地。 地址控制部分控制帧存储器中的写入地址。 行缓冲器写入控制部分根据图像旋转指令信号控制行缓冲器中的写入方向。