利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.027 秒)

    SEMICONDUCTOR INTEGRATED CIRCUIT FOR DISPLAYING IMAGE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT FOR DISPLAYING IMAGE 审中-公开
    用于显示图像的半导体集成电路

    公开(公告)号：US20110032262A1

    公开(公告)日：2011-02-10

    申请号：US12716782

    申请日：2010-03-03

    申请人： Toshiyuki Furusawa ,  Hitoshi Nemoto ,  Isao Ooigawa ,  Nariyuki Fukuda ,  Hiroyuki Fujioka ,  Noriyuki Moriyasu

    发明人： Toshiyuki Furusawa ,  Hitoshi Nemoto ,  Isao Ooigawa ,  Nariyuki Fukuda ,  Hiroyuki Fujioka ,  Noriyuki Moriyasu

    IPC分类号： G09G5/36

    CPC分类号： G09G5/395 ,  G06T1/60 ,  G09G5/36 ,  G09G5/393 ,  G09G2340/0492 ,  G09G2360/18

    摘要： A normal bus and an extension bus having the same bit width as the normal bus are provided. A line buffer has a plurality of line regions to store pixel data of input image data. A line buffer writing control portion controls a direction in which the pixel data is to be written to the line buffer. A line buffer reading control portion reads out the pixel data stored in the line buffer and to output the read out pixel data to the buses selectively. A frame memory writing control portion controls a destination in a frame memory to which the pixel data obtained from the buses is to be written. An address control portion controls a writing address in the frame memory. The line buffer writing control portion controls the writing direction in the line buffer in accordance with an image rotation command signal.

    摘要翻译： 提供具有与正常总线相同的位宽度的普通总线和扩展总线。 行缓冲器具有多个行区域以存储输入图像数据的像素数据。 行缓冲器写入控制部分控制将像素数据写入行缓冲器的方向。 行缓冲器读取控制部分读出存储在行缓冲器中的像素数据并选择性地将读出的像素数据输出到总线。 帧存储器写入控制部分控制要从总线获得的像素数据被写入的帧存储器中的目的地。 地址控制部分控制帧存储器中的写入地址。 行缓冲器写入控制部分根据图像旋转指令信号控制行缓冲器中的写入方向。

    Semiconductor integrated circuit deciding a power-supply voltage based on a delay test
    2.
    发明授权
    Semiconductor integrated circuit deciding a power-supply voltage based on a delay test 失效
    基于延迟测试决定电源电压的半导体集成电路

    公开(公告)号：US08598944B2

    公开(公告)日：2013-12-03

    申请号：US13556364

    申请日：2012-07-24

    申请人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

    发明人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

    IPC分类号： G11C5/14

    CPC分类号： G06F1/3296 ,  H03K19/0008 ,  Y02D10/172

    摘要： According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

    摘要翻译： 根据一个实施例，半导体集成电路包括半导体集成电路，提供规定电源电压的电压调节器，多个延迟测试电路，每个延迟测试电路被配置在响应于电流流动的每个区域中 对于每种运行模式，测试控制单元在逐步降低电源电压的同时在测试模式下使用延迟测试电路执行延迟测试，电源电压判定单元决定操作模式的电源电压 在延迟测试的基础上，存储单元存储每个操作模式的电源电压，电源电压配置单元从存储器单元读出与操作模式相对应的电源电压，以及供应配置单元布置 当每个操作模式开始执行时，电源电压作为电压调节器的输出电压。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    半导体集成电路

    公开(公告)号：US20130207692A1

    公开(公告)日：2013-08-15

    申请号：US13556364

    申请日：2012-07-24

    申请人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

    发明人： Nariyuki Fukuda ,  Noriyuki Moriyasu ,  Isao Ooigawa ,  Toshiyuki Furusawa ,  Satoko Kawakami ,  Hitoshi Nemoto ,  Hiroyuki Fujioka ,  Eiji Sawada ,  Tokio Tanaka

    IPC分类号： H03K5/153

    CPC分类号： G06F1/3296 ,  H03K19/0008 ,  Y02D10/172

    摘要： According to one embodiment, a semiconductor integrated circuit includes a semiconductor integrated circuit a voltage regulator providing a prescribed power-supply voltage, a plurality of delay test circuits, each of the delay test circuits being configured in each of areas where electrical current flows in response to each of operation modes, a test control unit executing a delay test using the delay test circuit under a test mode while decreasing a power-supply voltage in a stepwise fashion, a supply voltage decision unit deciding the power-supply voltage of the operation mode on a basis of the delay test, a memory unit storing the power-supply voltage of each operation mode, a supply voltage configuration unit reading out the power-supply voltage corresponding to the operation mode from the memory unit, and the supply configuration unit arranging the power-supply voltage as an output voltage of the voltage regulator when each of the operation modes starts to execute.

    摘要翻译： 根据一个实施例，半导体集成电路包括半导体集成电路，提供规定电源电压的电压调节器，多个延迟测试电路，每个延迟测试电路被配置在响应于电流流动的每个区域中 对于每种运行模式，测试控制单元在逐步降低电源电压的同时在测试模式下使用延迟测试电路执行延迟测试，电源电压判定单元决定操作模式的电源电压 在延迟测试的基础上，存储单元存储每个操作模式的电源电压，电源电压配置单元从存储器单元读出与操作模式相对应的电源电压，以及供应配置单元布置 当每个操作模式开始执行时，电源电压作为电压调节器的输出电压。

    Semiconductor integrated circuit device
    4.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20070075738A1

    公开(公告)日：2007-04-05

    申请号：US11502572

    申请日：2006-08-11

    申请人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    发明人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/1778

    摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.

    摘要翻译： 半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。 所述逻辑单元中的至少一个具有：包括MIS晶体管的标准单元，所述标准单元包括输入来自前一级的输出信号的输入端作为输入信号和输出端，所述标准单元执行 基于所述输入信号进行预定的逻辑运算，并输出所述逻辑运算的结果作为来自所述输出端子的输出信号; 设置在标准单元的输出端子与第一电源电压之间的第一导电型第一MIS晶体管，所述第一MIS晶体管包括输入电路控制信号的控制端子和提供电路控制信号的第一MIS晶体管 基于电路控制信号向标准单元的输出端施加第一电源电压，以使标准单元进入操作停止状态; 以及设置在所述标准单元和第二电源电压之间的第二导电型第二MIS晶体管，所述第二MIS晶体管包括输入所述电路控制信号的控制端子，所述第二MIS晶体管切断漏电流 的基于电路控制信号的标准单元中的MIS晶体管，以使标准单元进入操作停止状态。

    Semiconductor integrated circuit
    8.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06798238B2

    公开(公告)日：2004-09-28

    申请号：US10372937

    申请日：2003-02-26

    申请人： Munehito Mushiga ,  Katsuhiro Seta ,  Takeshi Yoshimoto ,  Toshiyuki Furusawa

    发明人： Munehito Mushiga ,  Katsuhiro Seta ,  Takeshi Yoshimoto ,  Toshiyuki Furusawa

    IPC分类号： H03L706

    CPC分类号： H03K19/0016

    摘要： A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line; a plurality of single logic circuits each including a plurality of transistors; a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits, said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.

    摘要翻译： 一种半导体集成电路，包括第一参考电压线; 第二参考电压线;多个单个逻辑电路，每个包括多个晶体管; 第一开关，其具有设置在所述第一参考电压线和所述逻辑电路之间的第一晶体管，所述第一晶体管的阈值电压高于逻辑电路中的晶体管; 以及具有第二晶体管的第二开关，所述第二晶体管设置在所述第二晶体管之间，具有比所述逻辑电路中的晶体管更高的阈值电压，所述第一和第二开关在所述单个逻辑电路中的至少一个处于操作时导通，同时 当所有单个逻辑电路都处于待机状态时，所述第一和第二开关断开。

    Semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08067962B2

    公开(公告)日：2011-11-29

    申请号：US12554570

    申请日：2009-09-04

    申请人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    发明人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    IPC分类号： H03K19/096

    CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/1778

    摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

    摘要翻译： 半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。 逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。 第一导电型第一MIS晶体管，其设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管， 基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。 第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。