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公开(公告)号：US08352531B2
公开(公告)日：2013-01-08
申请号：US12177346
申请日：2008-07-22
IPC分类号： G06F7/38
CPC分类号： G06F7/49947
摘要： The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case such as a disabled overflow exception. A disabled overflow exception may be detected by inspecting the normalized exponent. If a disabled overflow exception is detected, the round mode is selected to execute only in the non-increment data path thereby preventing the fraction increment data path from being selected.
摘要翻译： 强制浮点处理器的较圆形部分的结果或输出仅在舍入器内的分数非递增数据路径中发生，而不在舍入器内的分数增量数据路径中。 部分强制在角落外部活动，例如禁用的溢出异常。 可以通过检查归一化指数来检测到禁用的溢出异常。 如果检测到禁用的溢出异常，则选择循环模式仅在非增量数据路径中执行，从而防止分数增量数据路径被选择。
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公开(公告)号：US07849428B2
公开(公告)日：2010-12-07
申请号：US12107940
申请日：2008-04-23
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/505 , G06F2217/78
摘要： The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.
摘要翻译： 本发明提供了一种全自动的方法，用于获得由于时钟选通而具有最小功耗的电路。 要优化的电路设计被修改为减少功率修改的设计并且与时钟门控方案相关联。 验证工具将修改后的设计与原始设计进行比较，以确定是否可以使用修改后的设计。 可以重复进行进一步的修改，直到实现最佳设计。
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公开(公告)号：US20100023573A1
公开(公告)日：2010-01-28
申请号：US12177346
申请日：2008-07-22
IPC分类号： G06F7/38
CPC分类号： G06F7/49947
摘要： The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case such as a disabled overflow exception. A disabled overflow exception may be detected by inspecting the normalized exponent. If a disabled overflow exception is detected, the round mode is selected to execute only in the non-increment data path thereby preventing the fraction increment data path from being selected.
摘要翻译： 强制浮点处理器的较圆形部分的结果或输出仅在舍入器内的分数非递增数据路径中发生，而不在舍入器内的分数增量数据路径中。 部分强制在角落外部活动，例如禁用的溢出异常。 可以通过检查归一化指数来检测到禁用的溢出异常。 如果检测到禁用的溢出异常，则选择循环模式仅在非增量数据路径中执行，从而防止分数增量数据路径被选择。
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4.发明授权Methods and apparatus for monitoring power gating circuitry and for controlling circuit operations in dependence on monitored power gating conditions 失效监控电源门控电路的方法和装置，并根据受监控的电源门控条件控制电路运行公开(公告)号：US07679402B2
公开(公告)日：2010-03-16
申请号：US12062102
申请日：2008-04-03
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016
摘要： A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.
摘要翻译： 结合有当前饥饿的环形振荡器的电路被耦合到集成电路中的功率门开关。 结合当前饥饿的环形振荡器的电路放大与电源栅极开关和地之间的虚拟地之间的电压差，并将该差转换成频率。 数字逻辑使用计数器和参考时钟监视环形振荡器的输出。 控制电路根据与功率门开关相关的监控条件控制集成电路的工作。 一种方法监视集成电路中的电源门极开关上的虚拟接地电压; 并且根据所监视的虚拟接地电压来控制集成电路的操作。
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5.发明申请公开(公告)号：US20090251171A1
公开(公告)日：2009-10-08
申请号：US12062102
申请日：2008-04-03
IPC分类号： H03K17/16
CPC分类号： H03K19/0016
摘要： A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.
摘要翻译： 结合有当前饥饿的环形振荡器的电路被耦合到集成电路中的功率门开关。 结合当前饥饿的环形振荡器的电路放大与电源栅极开关和地之间的虚拟地之间的电压差，并将该差转换成频率。 数字逻辑使用计数器和参考时钟监视环形振荡器的输出。 控制电路根据与功率门开关相关的监控条件控制集成电路的工作。 一种方法监视集成电路中的电源门极开关上的虚拟接地电压; 并且根据所监视的虚拟接地电压来控制集成电路的操作。
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公开(公告)号：US20080288901A1
公开(公告)日：2008-11-20
申请号：US12107940
申请日：2008-04-23
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/505 , G06F2217/78
摘要： The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.
摘要翻译： 本发明提供了一种全自动的方法，用于获得由于时钟选通而具有最小功耗的电路。 要优化的电路设计被修改为减少功率修改的设计并且与时钟门控方案相关联。 验证工具将修改后的设计与原始设计进行比较，以确定是否可以使用修改后的设计。 可以重复进行进一步的修改，直到实现最佳设计。
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7.发明授权Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation 失效来自第二执行单元的多路复用输出用于复合计算的第一原始执行单元的较宽宽度中间结果的添加/饱和处理部分公开(公告)号：US07694112B2
公开(公告)日：2010-04-06
申请号：US12023432
申请日：2008-01-31
IPC分类号： G06F9/302
CPC分类号： G06F7/57 , G06F7/49921 , G06F9/30014 , G06F9/3893
摘要： A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.
摘要翻译： 根据示例性实施例提供了一种用于执行多个计算原语的方法。 第一计算单元和至少第二计算单元合作执行多个计算原语。 第一计算单元独立计算其他计算原语。 通过对共享源操作数总线或共享结果总线的仲裁，通过协作地执行多个计算原语所需的第一和第二计算单元的可用性通过用于在专用计算单元上执行的计算原语的预留处理来确保。
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8.发明申请METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL PRIMITIVES ON MULTIPLE EXECUTION UNITS 失效无冲突的方法，多个执行单位的计算原则的合作执行公开(公告)号：US20090198974A1
公开(公告)日：2009-08-06
申请号：US12023432
申请日：2008-01-31
CPC分类号： G06F7/57 , G06F7/49921 , G06F9/30014 , G06F9/3893
摘要： A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.
摘要翻译： 根据示例性实施例提供了一种用于执行多个计算原语的方法。 第一计算单元和至少第二计算单元合作执行多个计算原语。 第一计算单元独立计算其他计算原语。 通过对共享源操作数总线或共享结果总线的仲裁，通过协作地执行多个计算原语所需的第一和第二计算单元的可用性通过用于在专用计算单元上执行的计算原语的预留处理来确保。
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