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23 条记录 (耗时 0.027 秒)

    Methods and apparatus for monitoring power gating circuitry and for controlling circuit operations in dependence on monitored power gating conditions
    1.
    发明授权
    Methods and apparatus for monitoring power gating circuitry and for controlling circuit operations in dependence on monitored power gating conditions 失效
    监控电源门控电路的方法和装置，并根据受监控的电源门控条件控制电路运行

    公开(公告)号：US07679402B2

    公开(公告)日：2010-03-16

    申请号：US12062102

    申请日：2008-04-03

    申请人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

    发明人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/0016

    摘要： A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

    摘要翻译： 结合有当前饥饿的环形振荡器的电路被耦合到集成电路中的功率门开关。 结合当前饥饿的环形振荡器的电路放大与电源栅极开关和地之间的虚拟地之间的电压差，并将该差转换成频率。 数字逻辑使用计数器和参考时钟监视环形振荡器的输出。 控制电路根据与功率门开关相关的监控条件控制集成电路的工作。 一种方法监视集成电路中的电源门极开关上的虚拟接地电压; 并且根据所监视的虚拟接地电压来控制集成电路的操作。

    Methods and Apparatus for Monitoring Power Gating Circuitry and for Controlling Circuit Operations in Dependence on Monitored Power Gating Conditions
    2.
    发明申请
    Methods and Apparatus for Monitoring Power Gating Circuitry and for Controlling Circuit Operations in Dependence on Monitored Power Gating Conditions 失效
    监控电源门控和控制电路运行依赖于监控电源门控条件的方法和装置

    公开(公告)号：US20090251171A1

    公开(公告)日：2009-10-08

    申请号：US12062102

    申请日：2008-04-03

    申请人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

    发明人： J. Adam Butts ,  Gary S. Ditlow ,  Stephen V. Kosonocky ,  Brian C. Monwai

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0016

    摘要： A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

    摘要翻译： 结合有当前饥饿的环形振荡器的电路被耦合到集成电路中的功率门开关。 结合当前饥饿的环形振荡器的电路放大与电源栅极开关和地之间的虚拟地之间的电压差，并将该差转换成频率。 数字逻辑使用计数器和参考时钟监视环形振荡器的输出。 控制电路根据与功率门开关相关的监控条件控制集成电路的工作。 一种方法监视集成电路中的电源门极开关上的虚拟接地电压; 并且根据所监视的虚拟接地电压来控制集成电路的操作。

    Content addressable memory array programmed to perform logic operations
    6.
    发明授权
    Content addressable memory array programmed to perform logic operations 有权
    内容可寻址存储器阵列被编程为执行逻辑运算

    公开(公告)号：US08059438B2

    公开(公告)日：2011-11-15

    申请号：US12549740

    申请日：2009-08-28

    申请人： Leland Chang ,  Gary S. Ditlow ,  Brian L. Ji ,  Robert K. Montoye

    发明人： Leland Chang ,  Gary S. Ditlow ,  Brian L. Ji ,  Robert K. Montoye

    IPC分类号： G11C15/00

    CPC分类号： G11C15/046 ,  G11C7/1006 ,  G11C13/0004

    摘要： A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed.

    摘要翻译： 用于对两个或多个输入变量执行逻辑运算的存储器件包括匹配线和第一和第二存储器单元。 第一和第二存储单元集体地包括第一，第二，第三和第四存储元件。 第一，第二，第三和第四存储器元件可以具有在其中编程的第一值或第二值，并且其中基于特定逻辑功能将第一，第二，第三和第四存储器元件编程为高电阻值或低电阻值 被执行。

    Content addressable memory reference clock
    7.
    发明授权
    Content addressable memory reference clock 有权
    内容可寻址内存参考时钟

    公开(公告)号：US07948782B2

    公开(公告)日：2011-05-24

    申请号：US12549772

    申请日：2009-08-28

    申请人： Leland Chang ,  Gary S. Ditlow ,  Brian L. Ji ,  Robert K. Montoye

    发明人： Leland Chang ,  Gary S. Ditlow ,  Brian L. Ji ,  Robert K. Montoye

    IPC分类号： G11C15/00

    CPC分类号： G11C15/046 ,  G11C13/0004

    摘要： A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic.

    摘要翻译： 存储器系统包括包括多个匹配线的内容可寻址存储器（CAM），每个匹配线具有耦合到其上的多个存储器单元。 该系统还包括耦合到CAM的匹配检测器和具有耦合到其上的多个参考存储器单元的参考匹配线，参考存储器单元是相同类型的存储器单元。 该系统还包括耦合到参考匹配线的匹配线传感器和匹配检测器，其确定参考匹配线的特性，并且基于该特性向匹配检测器提供定时信号。

    Integrated circuit (IC) chip design method, program product and system
    8.
    发明授权
    Integrated circuit (IC) chip design method, program product and system 失效
    集成电路（IC）芯片设计方法，程序产品和系统

    公开(公告)号：US07552412B2

    公开(公告)日：2009-06-23

    申请号：US11274556

    申请日：2005-11-15

    申请人： Soroush Abbaspour ,  Gary S. Ditlow ,  Chandramouli V. Kashyap ,  Ruchir Puri

    发明人： Soroush Abbaspour ,  Gary S. Ditlow ,  Chandramouli V. Kashyap ,  Ruchir Puri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

    摘要翻译： 电路设计方法，计算机程序产品和芯片设计系统体现了该方法。 从电路设计中选择静态时序分析（STA）的门。 为所选择的门确定初始性能特征（例如负载和转换转换）。 从初始性能特性确定栅极的电荷等效有效电容（CQeff）。 在使用CQeff作为所选择的栅极的有效负载的栅极的单次通过中确定栅极延迟。 可选地，如果总栅极负载电容（Ctot）超过CQeff小于最小值，则确定有效电容（Ceff）并用于确定栅极延迟。

    Partitioning and load balancing graphical shape data for parallel applications
    9.
    发明授权
    Partitioning and load balancing graphical shape data for parallel applications 失效
    用于并行应用的分区和负载平衡图形形状数据

    公开(公告)号：US06788302B1

    公开(公告)日：2004-09-07

    申请号：US09631764

    申请日：2000-08-03

    申请人： Gary S. Ditlow ,  Daria R. Dooling ,  David E. Moran ,  Ralph J. Williams

    发明人： Gary S. Ditlow ,  Daria R. Dooling ,  David E. Moran ,  Ralph J. Williams

    IPC分类号： G06F1580

    CPC分类号： G06F9/5066

    摘要： The present invention divides a large graphics file into smaller “frames” of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

    摘要翻译： 本发明将大图形文件分割成更小的“帧”图形文件。 分割过程优选地在任意数量的处理器之间进行负载平衡。 这允许并行使用许多处理器来划分大图形文件，然后处理较小的输出帧。 此外，负载平衡以这样的方式执行，即只有图形文件的一部分需要被任何一个处理器加载。 这样可以节省内存和计算需求。 优选地，图形文件以三维方式分割，使得任何一个处理器将被分配一个三维块或图形文件的体积。 图形文件的三维分区将成为一帧，一个处理器访问图形文件，将其三维分区复制到新的输出帧中。

    CONTENT ADDRESSABLE MEMORY ARRAY WRITING
    10.
    发明申请
    CONTENT ADDRESSABLE MEMORY ARRAY WRITING 审中-公开
    内容可寻址存储阵列写

    公开(公告)号：US20110051485A1

    公开(公告)日：2011-03-03

    申请号：US12549761

    申请日：2009-08-28

    申请人： Leland Chang ,  Gary S. Ditlow ,  Brian L. Ji ,  Robert K. Montoye

    发明人： Leland Chang ,  Gary S. Ditlow ,  Brian L. Ji ,  Robert K. Montoye

    IPC分类号： G11C15/00 ,  G11C7/00 ,  G11C11/00

    CPC分类号： G11C15/00 ,  G11C13/0004 ,  G11C15/02 ,  G11C15/046

    摘要： A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array.

    摘要翻译： 用于存储一个或多个地址的存储器系统包括具有字线，位线，转置字线和转置位线的可转位存储器，并且接收并存储尺寸为M×N的输入阵列和读取的内容可寻址存储器（CAM） 转置存储器的转置字线，以形成输入字，并将输入字存储在N乘M阵列中。