公开(公告)号：US20130061022A1

公开(公告)日：2013-03-07

申请号：US13223489

申请日：2011-09-01

Applicant: JENQ KUEN LEE ,  CHI BANG KUAN

Inventor： JENQ KUEN LEE ,  CHI BANG KUAN

IPC: G06F15/76 ,  G06F9/06

CPC classification number: G06F8/441 ,  G06F9/3012 ,  G06F9/3891

Abstract: A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

Abstract translation: 一种用于为具有分布式寄存器文件的VLIW DSP处理器提供固有支持的方法包括以下步骤：根据DSP处理器的指令生成具有簇信息的程序表示，其中所述簇信息由具有簇固有编码的程序提供; 识别在程序表示中指示应用于不同数据集合上的并行指令序列的数据流操作; 识别指示由节目表示中的数据流操作共享的数据的数据共享关系; 识别指示从节目表示中的数据流操作聚合的结果的数据聚合关系; 并根据识别的数据流操作，数据共享关系和数据聚合关系为DSP处理器执行寄存器分配。

公开(公告)号：US20130191818A1

公开(公告)日：2013-07-25

申请号：US13354291

申请日：2012-01-19

Applicant: JENQ KUEN LEE ,  MING YU HUNG ,  YUAN SHIN HWANG ,  PENG SHENG CHEN

Inventor： JENQ KUEN LEE ,  MING YU HUNG ,  YUAN SHIN HWANG ,  PENG SHENG CHEN

IPC: G06F9/45

CPC classification number: G06F8/434

Abstract: A computer-implemented probabilistic pointer analysis method using SSA form comprises the steps of: evaluating a program in an SSA form comprising a target pointer to determine pointer relations between the target pointer, a plurality of aliased pointers related to the target pointer and at least a probable location of the target pointer; and generating a direct probabilistic relation between the target pointer and the at least a probable location of the target pointer according to the pointer relation.

Abstract translation: 使用SSA形式的计算机实现的概率指针分析方法包括以下步骤：评估包括目标指针的SSA形式的程序，以确定目标指针之间的指针关系，与目标指针相关的多个别名指针和至少一个 目标指针的可能位置; 以及根据所述指针关系，生成所述目标指针与所述目标指针的所述至少可能位置之间的直接概率关系。

公开(公告)号：US20130080141A1

公开(公告)日：2013-03-28

申请号：US13614263

申请日：2012-09-13

Applicant: JENQ KUEN LEE ,  PO YU CHEN ,  CHENG YEN LIN

Inventor： JENQ KUEN LEE ,  PO YU CHEN ,  CHENG YEN LIN

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F2217/78

Abstract: The current disclosure discloses a power aware simulation system comprising an embedded multi-core simulation module, a power abstract interpretation module and a C power estimation (CPE) power profiling module. The embedded multi-core simulation module comprises a plurality of digital signal processors (DSP), an external memory and a direct memory access. Each of the plurality of DSPs comprises a DSP core, an instruction cache and a local memory. The power abstract interpretation module is coupled to the plurality of DSPs, the external memory, the DMA and the CPE profiling module, respectively.

Abstract translation: 本公开公开了一种功率感知模拟系统，其包括嵌入式多核仿真模块，功率抽象解释模块和C功率估计（CPE）功率分析模块。 嵌入式多核仿真模块包括多个数字信号处理器（DSP），外部存储器和直接存储器存取。 多个DSP中的每一个包括DSP内核，指令高速缓存和本地存储器。 功率抽象解释模块分别耦合到多个DSP，外部存储器，DMA和CPE分析模块。

公开(公告)号：US20110087922A1

公开(公告)日：2011-04-14

申请号：US12576678

申请日：2009-10-09

Applicant: JENQ KUEN LEE ,  SHOU WEI CHANG

Inventor： JENQ KUEN LEE ,  SHOU WEI CHANG

IPC: G06F11/07

CPC classification number: G06F11/2242

Abstract: A test method for a master-slave concurrent system running on a multicore processor includes the steps of establishing a PFA, otherwise called probabilistic finite automata, or probabilistic finite state machine, for a given regular expression; generating test patterns by running the PFA; splitting and merging the test patterns to generate an interleaved test pattern; and performing test on the master-slave system according to the interleaved test pattern. In an embodiment, the method further includes a step of debugging failures of the multicore processor during testing.

Abstract translation: 用于在多核处理器上运行的主从同时系统的测试方法包括为给定正则表达式建立PFA（否则称为概率有限自动机）或概率有限状态机的步骤; 通过运行PFA生成测试模式; 分割和合并测试图案以产生交错的测试图案; 并根据交错的测试模式对主从系统进行测试。 在一个实施例中，该方法还包括在测试期间调试多核处理器的故障的步骤。

公开(公告)号：US20110083133A1

公开(公告)日：2011-04-07

申请号：US12571986

申请日：2009-10-01

Applicant: JENQ KUEN LEE ,  KUN YUAN HSIEH

Inventor： JENQ KUEN LEE ,  KUN YUAN HSIEH

IPC: G06F9/46 ,  G06F15/16

CPC classification number: G06F9/547 ,  G06F9/544

Abstract: A method of streaming remote procedure invocation for multi-core systems to execute a transmitting thread and an aggregating thread of a multi-core system comprises the steps of: temporarily storing data to be transmitted; activating the aggregating thread if the amount of the temporarily stored data is equal to or greater than a threshold and the aggregating thread is at pause status; pausing the transmitting thread if there is no space to temporarily store the data to be transmitted; retrieving data to be aggregated; activating the transmitting thread if the amount of the data to be aggregated is less than a threshold and the transmitting thread is at pause status; and pausing the aggregating thread if there is no data to be retrieved.

Abstract translation: 一种用于多核系统的远程过程调用的流程执行多核系统的发送线程和聚合线程的方法包括以下步骤：临时存储待发送的数据; 如果临时存储的数据量等于或大于阈值并且聚合线程处于暂停状态，则激活聚合线程; 如果没有空间临时存储要发送的数据，则暂停发送线程; 检索要聚合的数据; 如果要聚合的数据量小于阈值并且发送线程处于暂停状态，则激活发送线程; 并且如果没有要检索的数据，则暂停聚合线程。

公开(公告)号：US20100037037A1

公开(公告)日：2010-02-11

申请号：US12490932

申请日：2009-06-24

Applicant: JENQ KUEN LEE ,  LING HUA TSENG ,  CHUNG KAI CHEN

Inventor： JENQ KUEN LEE ,  LING HUA TSENG ,  CHUNG KAI CHEN

IPC: G06F9/40 ,  G06F9/44 ,  G06F9/30

CPC classification number: G06F9/3012 ,  G06F8/441 ,  G06F9/3885 ,  G06F9/3891

Abstract: A method for pipelining instructions on a PAC processor includes determining a minimum initial interval, and grouping the instructions so that the operands of dependent instructions are assigned to the same local register file. The virtual registers of the instructions that have data dependency across the first functional unit and the second functional unit are assigned to a global register file. The instructions are then modulo scheduled based on a current value of initial interval. The virtual registers of the scheduled instructions are allocated to the corresponding register files. If the allocation fails, a set of virtual registers is transferred from the first or second register file to the global register file.

Abstract translation: 用于在PAC处理器上流水线指令的方法包括确定最小初始间隔，并对指令进行分组，使得依赖指令的操作数被分配给相同的本地寄存器文件。 在第一功能单元和第二功能单元之间具有数据依赖性的指令的虚拟寄存器被分配给全局寄存器文件。 然后根据初始间隔的当前值对指令进行模数调度。 调度指令的虚拟寄存器被分配给相应的寄存器文件。 如果分配失败，则一组虚拟寄存器从第一或第二寄存器文件传输到全局寄存器文件。

公开(公告)号：US20130024666A1

公开(公告)日：2013-01-24

申请号：US13184857

申请日：2011-07-18

Applicant: JENQ KUEN LEE ,  YU TE LIN ,  CHUNG JU WU

Inventor： JENQ KUEN LEE ,  YU TE LIN ,  CHUNG JU WU

IPC: G06F9/312

CPC classification number: G06F9/3012 ,  G06F9/3836 ,  G06F9/3891

Abstract: A method of scheduling a plurality of instructions for a processor comprises the steps of: establishing a functional unit resource table comprising a plurality of columns, each of which corresponds to one of a plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a functional unit of the processor; establishing a ping-pong resource table comprising a plurality of columns, each of which corresponds to one of the plurality of operation cycles of the processor and comprises a plurality of fields, each of which indicates a read port or a write port of a register bank of the processor; and allotting the plurality of instructions to the plurality of operation cycles of the processor and registering the functional units and the ports of the register banks corresponding to the allotted instructions on the functional unit resource table and the ping-pong resource table.

Abstract translation: 一种为处理器调度多个指令的方法包括以下步骤：建立包括多个列的功能单元资源表，每个列对应于处理器的多个操作周期中的一个，并且包括多个字段， 其中的每一个表示处理器的功能单元; 建立包括多个列的乒乓资源表，每个列对应于处理器的多个操作周期中的一个，并且包括多个字段，每个字段指示寄存器组的读端口或写端口 的处理器; 以及将所述多个指令分配给所述处理器的所述多个操作周期，并且将对应于所述分配指令的所述寄存器组的功能单元和端口注册在所述功能单元资源表和所述乒乓资源表上。

公开(公告)号：US20120159110A1

公开(公告)日：2012-06-21

申请号：US12974291

申请日：2010-12-21

Applicant: CHUNG JU WU ,  YU TE LIN ,  JENQ KUEN LEE

Inventor： CHUNG JU WU ,  YU TE LIN ,  JENQ KUEN LEE

IPC: G06F12/02

CPC classification number: G06F9/3891

Abstract: A method of allocating registers for a processor based on cycle information is disclosed. The processor comprises a first cluster and a second cluster. Each cluster comprises a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment are performed to take full advantage of the properties of a processor as well as cycle information.

Abstract translation: 公开了一种基于周期信息为处理器分配寄存器的方法。 处理器包括第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件，以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用处理器的属性 作为循环信息。