公开(公告)号：US11775831B2

公开(公告)日：2023-10-03

申请号：US18154727

申请日：2023-01-13

申请人： Jae-sun Seo ,  Minkyu Kim

发明人： Jae-sun Seo ,  Minkyu Kim

IPC分类号： G06N3/08 ,  G06N3/045 ,  G06N3/0464 ,  G06F7/48

CPC分类号： G06N3/08 ,  G06F7/48 ,  G06N3/045 ,  G06N3/0464

摘要： Techniques are described for efficiently reducing the amount of total computation in convolutional neural networks (CNNs) without affecting the output result or classification accuracy. Computation redundancy in CNNs is reduced by exploiting the computing nature of the convolution and subsequent pooling (e.g., sub-sampling) operations. In some implementations, the input features may be divided into a group of precision values and the operation(s) may be cascaded. A maximum may be identified (e.g., by 90% probability) using a small number of bits in the input features, and the full-precision convolution may then be performed on the maximum input. Accordingly, the total number of bits used to perform the convolution is reduced without affecting the output features or the final classification accuracy.

公开(公告)号：US20220318628A1

公开(公告)日：2022-10-06

申请号：US17714677

申请日：2022-04-06

申请人： Sai Kiran Cherupally ,  Jian Meng ,  Shihui Yin ,  Deliang Fan ,  Jae?sun Seo

发明人： Sai Kiran Cherupally ,  Jian Meng ,  Shihui Yin ,  Deliang Fan ,  Jae?sun Seo

IPC分类号： G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G06F7/544

摘要： Hardware noise-aware training for improving accuracy of in-memory computing (IMC)-based deep neural network (DNN) hardware is provided. DNNs have been very successful in large-scale recognition tasks, but they exhibit large computation and memory requirements. To address the memory bottleneck of digital DNN hardware accelerators, IMC designs have been presented to perform analog DNN computations inside the memory. Recent IMC designs have demonstrated high energy-efficiency, but this is achieved by trading off the noise margin, which can degrade the DNN inference accuracy. The present disclosure proposes hardware noise-aware DNN training to largely improve the DNN inference accuracy of IMC hardware. During DNN training, embodiments perform noise injection at the partial sum level, which matches with the crossbar structure of IMC hardware, and the injected noise data is directly based on measurements of actual IMC prototype chips.

公开(公告)号：US20210082502A1

公开(公告)日：2021-03-18

申请号：US16921198

申请日：2020-07-06

申请人： Jae-sun Seo ,  Shimeng Yu

发明人： Jae-sun Seo ,  Shimeng Yu

IPC分类号： G11C13/00 ,  G06N3/02 ,  G11C7/18 ,  G11C11/54 ,  G11C7/10

摘要： A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

公开(公告)号：US10360496B2

公开(公告)日：2019-07-23

申请号：US15088543

申请日：2016-04-01

申请人： Gregory K. Chen ,  Jae-Sun Seo ,  Thomas C Chen ,  Raghavan Kumar

发明人： Gregory K. Chen ,  Jae-Sun Seo ,  Thomas C Chen ,  Raghavan Kumar

IPC分类号： G06N3/063 ,  G06N3/04

摘要： An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.

公开(公告)号：US20170286827A1

公开(公告)日：2017-10-05

申请号：US15088543

申请日：2016-04-01

申请人： GREGORY K. CHEN ,  JAE-SUN SEO ,  THOMAS C CHEN ,  RAGHAVAN KUMAR

发明人： GREGORY K. CHEN ,  JAE-SUN SEO ,  THOMAS C CHEN ,  RAGHAVAN KUMAR

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/049

摘要： An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.

公开(公告)号：US20160336064A1

公开(公告)日：2016-11-17

申请号：US15156113

申请日：2016-05-16

申请人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

发明人： Jae-sun Seo ,  Shimeng Yu ,  Yu Cao ,  Sarma Vrudhula

IPC分类号： G11C13/00 ,  G06N3/08

CPC分类号： G06N3/088 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0069

摘要： Neuromorphic computational circuitry is disclosed that includes a cross point resistive network and line control circuitry. The cross point resistive network includes variable resistive units. One set of the variable resistive units is configured to generate a correction line current on a conductive line while other sets of the variable resistive units generate resultant line currents on other conductive lines. The line control circuitry is configured to receive the line currents from the conductive lines and generate digital vector values. Each of the digital vector values is provided in accordance with a difference between the current level of a corresponding resultant line current and a current level of the correction line current. In this manner, the digital vector values are corrected by the current level of the correction line current in order to reduce errors resulting from finite on to off conductance state ratios.

摘要翻译： 公开了包括交叉点电阻网络和线路控制电路的神经计算电路。 交叉点电阻网络包括可变电阻单元。 一组可变电阻单元被配置为在导线上产生校正线电流，而其他组的可变电阻单元在其它导线上产生合成线电流。 线路控制电路被配置为从导线接收线电流并产生数字矢量值。 根据对应的合成线电流的电流电平和校正线电流的电流电平之间的差，提供每个数字矢量值。 以这种方式，通过校正线电流的当前电平来校正数字矢量值，以便减少由有限导通到导通状态比率导致的误差。

公开(公告)号：US20230070387A1

公开(公告)日：2023-03-09

申请号：US17986652

申请日：2022-11-14

申请人： Jae-sun Seo ,  Shimeng Yu

发明人： Jae-sun Seo ,  Shimeng Yu

IPC分类号： G11C13/00 ,  G06N3/02 ,  G11C7/18 ,  G11C11/54 ,  G11C7/10

摘要： A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

公开(公告)号：US20170300815A1

公开(公告)日：2017-10-19

申请号：US15487117

申请日：2017-04-13

申请人： Jae-sun Seo

发明人： Jae-sun Seo

IPC分类号： G06N3/08 ,  G06N3/04

CPC分类号： G06N3/08 ,  G06N3/063

摘要： An information processing system, which includes a control system and an artificial neural network, is disclosed. The artificial neural network includes a group of neurons and a group of synapses, which includes a first portion and a second portion. The control system selects one of a group of operating modes. The group of neurons processes information. The group of synapses provide connectivity to each of the group of neurons. During a first operating mode of the group of operating modes, the first portion of the group of synapses is enabled and the second portion of the group of synapses is enabled. During a second operating mode of the group of operating modes, the first portion of the group of synapses is enabled and the second portion of the group of synapses is disabled.

公开(公告)号：US20160049195A1

公开(公告)日：2016-02-18

申请号：US14824782

申请日：2015-08-12

申请人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

发明人： Shimeng Yu ,  Yu Cao ,  Jae-sun Seo ,  Sarma Vrudhula ,  Jieping Ye

IPC分类号： G11C13/00

CPC分类号： G11C13/0026 ,  G11C5/06 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/77 ,  G11C2213/79

摘要： This disclosure relates generally to resistive memory systems. The resistive memory systems may be utilized to implement neuro-inspired learning algorithms with full parallelism. In one embodiment, a resistive memory system includes a cross point resistive network and switchable paths. The cross point resistive network includes variable resistive elements and conductive lines. The conductive lines are coupled to the variable resistive elements such that the conductive lines and the variable resistive elements form the cross point resistive network. The switchable paths are connected to the conductive lines so that the switchable paths are operable to selectively interconnect groups of the conductive lines such that subsets of the variable resistive elements each provide a combined variable conductance. With multiple resistive elements in the subsets, process variations in the conductances of the resistive elements average out. As such, learning algorithms may be implemented with greater precision using the cross point resistive network.

摘要翻译： 本公开一般涉及电阻式存储器系统。 电阻式存储器系统可用于实现具有完全并行性的神经启发式学习算法。 在一个实施例中，电阻式存储器系统包括交叉点电阻网络和可切换路径。 交叉点电阻网络包括可变电阻元件和导线。 导线耦合到可变电阻元件，使得导线和可变电阻元件形成交叉电阻网络。 可切换路径连接到导线，使得可切换路径可操作以选择性地互连导电线组，使得可变电阻元件的子集各自提供组合的可变电导。 在子集中具有多个电阻元件，电阻元件的电导的工艺变化平均。 因此，可以使用交叉点电阻网络以更高的精度来实现学习算法。

公开(公告)号：US07913101B2

公开(公告)日：2011-03-22

申请号：US11824410

申请日：2007-06-29

申请人： Himanshu Kaul ,  Jae-sun Seo ,  Ram K. Krishnamurthy

发明人： Himanshu Kaul ,  Jae-sun Seo ,  Ram K. Krishnamurthy

IPC分类号： G06F1/12

CPC分类号： H03K5/135 ,  H03K2005/00058 ,  H03K2005/00234 ,  H03K2005/00241

摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。